mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 102

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mc68hc08qa24

Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Error Detection Central Processor Unit (EDC)
8.5 FLT Pin
8.6 EDC Control Register
Technical Data
100
Address: $FE09
This pin is unaffected by all resets except for the error detect reset. On
the occurrence of a mismatch between the CPU and the EDC on any
address or data, the pin is driven to a logic 0 and remains low until it is
cleared by storing a 0 to bit 7of the EDC control register.
The control register for the EDC is shown in
register are used to simulate an error condition in each of the compare
circuits. When a write to the register is done, it is followed by an internal
reset if the data to any of the three control bits is a logic 1.
SFLTP — Set FLT Pin
FDB — Force Data Bus Bit
Reset:
Read:
Write:
This bit always reads as a 0. A logic 1 is set on the occurrence of an
error detect reset. It is cleared by writing a 0.
Writing a 1 to this bit forces the output of the data bus compare to
generate a reset. The bit will be set on failure to compare data.
Error Detection Central Processor Unit (EDC)
1 = Generate reset
0 = No reset
SFLTP
Bit 7
R
0
1
Figure 8-2. EDC Control Register (EDCR)
= Reserved
R
6
R
5
0
0
R
4
0
0
R
3
1
Figure
FDB
Freescale Semiconductor
2
0
8-2. The bits in this
MC68HC08QA24
FABH
1
0
FABL
Bit 0
0

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