mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 185

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.6 IRQ Module During Break Interrupts
MC68HC08QA24
Freescale Semiconductor
NOTE:
The vector fetch or software clear and the return of the IRQ pin to logic 1
can occur in any order. The interrupt request remains pending as long
as the IRQ pin is at logic 0. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the branch if interrupt pin is high (BIH) or branch if interrupt pin is
low (BIL) instruction to read the logic level on the IRQ pin.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
The system integration module (SIM) controls whether the IRQ interrupt
latch can be cleared during the break state. The BCFE bit in the SIM
break flag control register (SBFCR) enables software to clear the latches
during the break state. (See
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
•
request. If the IRQ mask bit, IMASK, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and
$FFFB.
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic
0, the IRQ latch remains set.
External Interrupt (IRQ)
10.8.3 SIM Break Flag Control
External Interrupt (IRQ)
Technical Data
Register.)
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