mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 324

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface B (TIMB)
21.5 Interrupts
21.6 Low-Power Modes
Technical Data
322
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H–TBCH0L)
initially control the buffered PWM output. TIMB status control register 0
(TBSCR0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMB overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0 percent duty
cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100 percent duty cycle output. (See
TIMB Channel Status and Control
These TIMB sources can generate interrupt requests:
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
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TIMB overflow flag (TOF) — The TOF bit is set when the TIMB
counter value rolls over to $0000 after matching the value in the
TIMB counter modulo registers. The TIMB overflow interrupt
enable bit, TOIE, enables TIMB overflow CPU interrupt requests.
TOF and TOIE are in the TIMB status and control register.
TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMB CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
Timer Interface B (TIMB)
Registers.)
Freescale Semiconductor
MC68HC08QA24
21.9.4