mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 217

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

17.4.6 Idle Characters
17.4.7 Inversion of Transmitted Output
17.4.8 Transmitter Interrupts
MC68HC08QA24
Freescale Semiconductor
NOTE:
An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit (mode character length) in
SCC1. The preamble is a synchronizing idle character that begins every
transmission.
If the TE bit (transmitter enable) is cleared during a transmission, the
PTE0/TxD pin becomes idle after completion of the transmission in
progress. Clearing and then setting the TE bit during a transmission
queues an idle character to be sent after the character currently being
transmitted.
When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the PTE0/TxD pin. Setting
TE after the stop bit appears on PTE0/TxD causes data previously
written to the SCDR to be lost.
A good time to toggle the TE bit is when the SCTE bit becomes set and
just before writing the next byte to the SCDR.
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
(See
These conditions can generate CPU interrupt requests from the SCI
transmitter:
•
17.9.1 SCI Control Register
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE (SCC2),
enables the SCTE bit to generate transmitter CPU interrupt
requests.
Serial Communications Interface (SCI)
1.)
Serial Communications Interface (SCI)
Technical Data
215