mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 259

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mc68hc08qa24

Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
18.8 Interrupts
MC68HC08QA24
Freescale Semiconductor
NOTE:
NOTE:
transmission begins when the SPSCK leaves its idle level and SS is
already low. The transmission continues until the SPSCK returns to its
IDLE level after the shift of the last data bit. (See
Formats.)
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0)
and later unselected (SS is at logic 1) even if no SPSCK is sent to that
slave. This happens because SS at logic 0 indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later unselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by toggling the SPE bit of the slave.
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if a transmission has begun.
To clear the MODF flag, read the SPSCR and then write to the SPCR
register. This entire clearing procedure must occur with no MODF
condition existing or else the flag will not be cleared.
The four SPI status flags shown in
generate CPU interrupt requests:.
SPTE (transmitter empty)
SPRF (receiver full)
OVRF (overflow)
MODF (mode fault)
Flag
Serial Peripheral Interface (SPI)
Table 18-3. SPI Interrupts
SPI transmitter CPU interrupt request (SPTIE = 1)
SPI receiver/error interrupt request (SPRIE = 1,
SPI receiver/error interrupt request (SPRIE = 1,
SPI receiver CPU interrupt request (SPRIE = 1)
ERRIE = 1)
ERRIE = 1, MODFEN = 1)
Table 18-3
Request
Serial Peripheral Interface (SPI)
can be enabled to
18.6 Transmission
Technical Data
257

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