mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 155

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

11.4.1 Polled LVI Operation
11.4.2 Forced Reset Operation
11.4.3 False Reset Protection
11.5 LVI Status Register
MC68HC08QA24
Freescale Semiconductor
Address
In applications that can operate at V
software can monitor V
register, the LVIPWR bit must be at logic 0 to enable the LVI module, and
the LVIRST bit must be at logic 1 to disable LVI resets.
In applications that require V
enabling LVI resets allows the LVI module to reset the MCU when V
falls to the LVI
more consecutive CPU cycles. In the configuration register, the LVIPWR
and LVIRST bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
The V
supply noise. For the LVI module to reset the MCU, V
or below the LVI
must be above LVI
reset.
The LVI status register (LVISR) flags V
level.
Reset:
Read: LVIOUT
Write:
DD
$FE0F
Bit 7
pin level is digitally filtered to reduce false resets due to power
R
R
0
Figure 11-2. LVI Status Register (LVISR)
Low-Voltage Inhibit (LVI)
TRIPF
= Reserved
TRIPF
R
6
0
0
TRIPR
level and remains at or below that level for nine or
level for nine or more consecutive CPU cycles. V
DD
for only one CPU cycle to bring the MCU out of
by polling the LVIOUT bit. In the configuration
R
5
0
0
DD
to remain above the LVI
R
4
0
0
DD
levels below the LVI
DD
voltages below the LVI
R
3
0
0
R
2
0
0
Low-Voltage Inhibit (LVI)
DD
TRIPF
must remain at
R
1
0
0
Technical Data
TRIPF
level,
level,
TRIPF
Bit 0
R
0
0
153
DD
DD