mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 285

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mc68hc08qa24

Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC08QA24
Freescale Semiconductor
NOTE:
ADICLK — ADC Input Clock Register Bit
During the conversion process, changing the ADC clock will result in an
incorrect conversion.
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at
approximately 1 MHz, correct operation can be guaranteed. (See
23.7 ADC
1 = Internal bus clock
0 = External clock (CGMXCLK)
Analog-to-Digital Converter (ADC)
X = don’t care
Characteristics.)
ADIV2
1 MHz = 
0
0
0
0
1
Table 19-2. ADC Clock Divide Ratio
ADIV1
X
0
0
1
1
f
XCLK
ADIV0
or bus frequency
ADIV[2:0]
X
0
1
0
1
ADC input clock / 16
ADC input clock / 1
ADC input clock / 2
ADC input clock / 4
ADC input clock / 8
ADC Clock Rate
Analog-to-Digital Converter (ADC)
Technical Data
283

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