mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 270

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mc68hc08qa24

Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Serial Peripheral Interface (SPI)
18.14.2 SPI Status and Control Register
Technical Data
268
SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable Bit
SPTIE— SPI Transmit Interrupt Enable Bit
The SPI status and control register contains flags to signal these
conditions:
The SPI status and control register also contains bits that perform these
functions:
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. (See
the SPE bit.
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow
error)
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
Serial Peripheral Interface (SPI)
18.10 Resetting the
Freescale Semiconductor
SPI.) Reset clears
MC68HC08QA24

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