mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 111

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

9.4.2.2 Acquisition and Tracking Modes
9.4.2.3 Manual and Automatic PLL Bandwidth Modes
MC68HC08QA24
Freescale Semiconductor
The PLL filter is manually or automatically configurable into one of two
operating modes:
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See
interrupts are enabled, the software can wait for a PLL interrupt request
and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL startup, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
to use as the source for the base clock. (See
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
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•
Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO (see
Acquisition/Lock Time
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register (see
Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO (see
Acquisition/Lock Time
tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct,
such as when the PLL is selected as the base clock source (see
9.4.3 Base Clock Selector
tracking mode when not in acquisition mode or when the ACQ bit
is set.
Clock Generator Module (CGM)
9.6.2 PLL Bandwidth Control
9.6.2 PLL Bandwidth Control
Information). This mode is used at PLL
Information). PLL jitter is much lower in
Circuit). The PLL is automatically in
9.4.3 Base Clock Selector
Clock Generator Module (CGM)
23.11 CGM
Register.) If PLL
Register).
23.11 CGM
Technical Data
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