mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 257

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MC68HC08QA24
Freescale Semiconductor
READ SPSCR
SPI RECEIVE
READ SPDR
COMPLETE
Figure 18-9. Clearing SPRF When OVRF Interrupt Is Not Enabled
OVRF
SPRF
1
2
3
4
5
6
7
BYTE 1
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
1
The first part of
to clear the SPRF without problems. However, as illustrated by the
second transmission example, the OVRF flag can be set in between the
time that SPSCR and SPDR are read.
In this case, an overflow can be easily missed. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it will not be
obvious that bytes are being lost as more transmissions are completed.
To prevent this, either enable the OVRF interrupt or do another read of
the SPSCR after the read of the SPDR. This ensures that the OVRF was
not set before the SPRF was cleared and that future transmissions will
complete with an SPRF interrupt.
Generally, to avoid this second SPSCR read, enable the OVRF to the
CPU by setting the ERRIE bit (SPSCR).
2
3
Serial Peripheral Interface (SPI)
4
BYTE 2
Figure 18-8
5
BYTE 3
6
shows how to read the SPSCR and SPDR
7
10
11
12
13
14
8
9
8
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
Figure 18-9
9
BYTE 4
10
11
Serial Peripheral Interface (SPI)
illustrates this process.
12
13
Technical Data
14
255