pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 142

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

bit oriented message (BOM) receiver are switched on/off independently. If the FALC
is used for HDLC formats only, the BOM receiver has to be switched off. If HDLC and
BOM receiver have been switched on (MODE.HRAC/BRAC), an automatic switching
between HDLC and BOM mode is enabled. If eight or more consecutive ones are
detected, the BOM mode is entered. Upon detection of a flag in the data stream, the
FALC
assumed (the left most bit is received first): 111111110xxxxxx0
Three different BOM reception modes can be programmed (CCR1.BRM+ CCR2.RBFE).
If CCR2.RFBE is set, the BOM receiver accepts only BOM frames after detecting 7 out
of 10 equal BOM pattern. Buffering of receive data is done in a 64 byte deep RFIFO.
5.1.15.6 4 kbit/s Data Link Access in F72 Format (T1/J1)
The DL-channel protocol is supported as follows:
•
•
5.2
5.2.1
Activated with bit FMR1.PMOD = 1.
PCM line bit rate
Single frame length
Framing frequency
Organization
Selection of one of the four permissible framing formats is performed by bits
FMR4.FM1/0. These formats are:
F4
F12
ESF
F72
The operating mode of the FALC
and characteristics, line code, multiframe structure, and signaling scheme.
The FALC
(T1/J1, 1.544 Mbit/s) carriers. The internal HDLC controller supports all signaling
procedures including signaling frame synchronization/synthesis in all framing formats.
User’s Manual
Hardware Description
Access is done on a multiframe basis through registers RDL(3:1),
The DL-bit information from frame 26 to 72 is stored in the receive FIFO of the
signaling controller.
®
56 switches back to HDLC mode. In BOM mode, the following byte format is
:
:
:
:
®
Framer Operating Modes (T1/J1)
General
56 implements all of the standard and/or common framing structures PCM24
4-frame multiframe
12-frame multiframe (D4)
Extended Superframe (F24)
72-frame multiframe (SLC96)
:
:
:
:
1.544 Mbit/s
193 bit, No. 1…193
8 kHz
24 time slots, No. 1…24
with 8 bits each, No. 1…8 and one preceding F-bit
®
56 is selected by programming the carrier data rate
142
Functional Description T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
®
56
56