pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 249

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

RCO(10:8)
Receive Control 1 (Read/Write)
Value after reset: 9C
RC1
RCO(7:0)
User’s Manual
Hardware Description
RCO7
7
Receive Offset/Receive Frame Marker Offset
Depending on the RP(A to D) pin function different offsets can be
programmed. The SYPR and the RFM pin function cannot be
selected in parallel.
Receive Offset (PC(4:1).RPC(2:0) = 000)
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse on port SYPR is active.
Calculation of delay time T (SCLKR cycles) depends on the value X
of the receive offset register RC(1:0). For programing refer to register
RC1.
Receive Frame Marker Offset (PC(4:1).RPC(2:0) = 001
Offset programming of the receive frame marker which is output on
port SYPR. The receive frame marker can be activated during any bit
position of the current frame.
Calculation of the value X of the receive offset register RC(1:0)
depends on the bit position which should be marked and SCLKR.
Refer to register RC1.
Receive Offset/Receive Frame Marker Offset
Depending on the RP(A to D) pin function different offsets can be
programmed. The SYPR and the RFM pin function cannot be
selected in parallel.
Receive Offset (PC(4:1).RPC(2:0) = 000)
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse on port SYPR is active.
Calculation of delay time T (SCLKR cycles) depends on the value X
of the receive offset register RC(1:0):
0 ≤T ≤4: X = 4 - T
5 ≤T ≤maximum delay:X = 2052 - T
with maximum delay = (256× SC/SD) -1
with SC = system clock defined by SIC1.SSC(1:0)
with SD = system data rate
H
249
DS1.1, 2003-10-23
PEF 2256 H/E
RCO0
E1 Registers
0
B
FALC
)
(25)
®
56