pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 20

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

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Signaling Controller
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Microprocessor Interface
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User’s Manual
Hardware Description
Programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass
Provides different time slot mapping modes
Supports fractional E1 or T1/J1 access
Flexible transparent modes
Pseudo-random binary sequence generator and monitor
(framed or unframed)
Clear channel capabilities (T1/J1)
Loop-timed mode
Three HDLC controllers
Bit stuffing, CRC check and generation, flag generation, flag and address
recognition, handling of bit oriented functions
Each HDLC controller selectable to operate on either line or system side
Supports signaling system #7
delimitation, alignment and error detection according to ITU-Q.703
processing of fill in signaling units, processing of errored signaling units
CAS/CAS-BR controller with last look capability, enhanced CAS-register access and
freeze signaling indication
DL-channel protocol for ESF format according to ANSI T1.403 specification or
according to AT&T TR54016 (T1/J1)
DL-bit access for F72 (SLC96) format (T1/J1)
Generates periodical performance report according to ANSI T1. 403
Provides access to serial signaling data streams
Multiframe synchronization and synthesis according to ITU-T G.732
Alarm insertion and detection (AIS and LOS in time slot 16)
Transparent mode
FIFO buffers (64 bytes deep) for efficient transfer of data packets
Time slot assignment
Any combination of time slots selectable for data transfer independent of signaling
mode (useful for fractional T1/J1 applications)
Time-slot 0 S
HDLC access to any S
8/16-bit microprocessor bus interface (Intel or Motorola type)
All registers directly accessible (byte or word access)
Multiplexed and non-multiplexed address bus operations
Hard/software reset options
Extended interrupt capabilities
a
8...4-bit handling via FIFOs (E1)
a
-bit combination (E1)
20
(TR62411)
DS1.1, 2003-10-23
PEF 2256 H/E
(TR54016)
Introduction
FALC
®
56