pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 227

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 61
Address
A8
AF
After reset all control registers except the XFIFO and XS(16:1) are initialized to defined
values. Unused bits have to be cleared (logical "0").
Note: Read access to unused register addresses: value should be ignored.
9.2
Transmit FIFO - HDLC Channel 1 (Write)
XFIFO
XFIFO
Writing data to XFIFO of HDLC channel 1 can be done in 8-bit (byte) or 16-bit (word)
access. The LSB is transmitted first.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO following a XPR
interrupt.
Command Register (Write)
Value after reset: 00
CMDR
RMC
RRES
User’s Manual
Hardware Description
Write access to unused register addresses: should be avoided, or set to 00
address range up to AF
defined elsewhere
XF15
RMC
XF7
Detailed Description of E1 Control Registers
7
7
E1 Control Register Address Arrangement (cont’d)
Receive Message Complete - HDLC Channel 1
Confirmation from CPU to FALC
block has been fetched following a RPF or RME interrupt, thus the
occupied space in the RFIFO can be released. If RMC is given while
RFIFO is already cleared, the next incoming data block is cleared
instantly, although interrupts are generated.
Receiver Reset
RRES
H
GLC1
Register
TPC0
XREP
H
; must be avoided in address range above AF
Type
R/W
R/W
XRES
227
Comment
Test Pattern Control Register 0
Global Line Control Register 1
XHF
®
56 that the current frame or data
XTF
XME
DS1.1, 2003-10-23
PEF 2256 H/E
SRES
XF0
XF8
E1 Registers
0
0
FALC
Page
297
298
H
(00)
(01)
(02)
if not
®
H
56
in