pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 399

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Global Configuration Register (Read/Write)
Value after reset: 00
GCR
VIS
SCI
SES
ECMC
PD
User’s Manual
Hardware Description
VIS
7
Masked Interrupts Visible
0 =
1 =
Status Change Interrupt
0 =
1 =
Select External Second Timer
0 =
1 =
Error Counter Mode COFA
0 =
1 =
Power Down
Switches between power-up and power-down mode.
0 =
1 =
SCI
Masked interrupt status bits are not visible in registers ISR(5:0).
Interrupts are generated either on activation or deactivation of
the internal interrupt source.
The following interrupts are activated both on activation and
deactivation of the internal interrupt source:
ISR2.LOS, ISR2.AIS and ISR0.PDEN
Internal second timer selected
External second timer selected
Not defined; reserved for future applications.
A Change of Frame or Multiframe Alignment COFA is detected
since the last resynchronization. The events are accumulated
in the COFA event counter COEC.(1:0).
Multiframe periods received in the asynchronous state are
accumulated in the COFA event counter COEC.(7:2).
An overflow of each counter is disabled.
Power up
Power down
All outputs are driven inactive, except the multifunction ports,
which are weakly driven high by the internal pullup devices.
Masked interrupt status bits are visible in ISR(5:0), but they are
not visible in registers GIS.
SES
ECMC
399
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
PD
0
FALC
(46)
®
56