pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 32

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin or
Ball No.
7 (D4)
User’s Manual
Hardware Description
Name
XL1
XDOP
XOID
Pin Definitions - Line Interface (cont’d)
Pin
Type
O
O
O
Buffer
Type
analog Transmit Line 1
digital
digital
Function
Analog output to the external transformer.
Selected if LIM1.DRS = 0
pin is in high-impedance state until bit
FMR0.XC1 = 1
More details about tristate modes are shown
in
Transmit Data Output Positive
This digital output for transmitted dual-rail
PCM(+) route signals can provide
•
•
The data is clocked with positive transitions of
XCLK in both cases. Output polarity is
selected by bit LIM0.XDOS (active low by
default). The dual-rail mode is selected if
LIM1.DRS = 1
reset this pin is in high-impedance state until
register LIM1.DRS = 1
Transmit Optical Interface Data
Unipolar data sent to a fiber-optical interface
with 2048 kbit/s (E1) or 1544 kbit/s (T1/J1)
which is clocked on the positive transitions of
XCLK. Clocking of NRZ-coded data is done
with 100% duty cycle. CMI-coded data is
shifted out with 50 % or 100 % duty cycle on
both transitions of XCLK according to the CMI
coding. Output polarity is selected by bit
LIM0.XDOS (active high by default). The
single-rail mode is selected if LIM1.DRS = 1
and FMR0.XC1 = 0
high-impedance state until register
LIM1.DRS = 1
32
Table 53/Table
half bauded signals with 50% duty cycle
(LIM0.XFB = 0
full bauded signals with 100% duty cycle
(LIM0.XFB = 1
B
B
B
and FMR0.XC1 = 1
and XPM2.XLT = 0
and XPM2.XLT = 0
B
B
60.
) or
)
B
. After reset this pin is in
B
and XPM2.XLT = 0
B
. After reset this
External Signals
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
B
B
B
.
. After
.
®
56
B
B
.