pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 353

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Common Configuration Register 1 (Read/Write)
Value after reset: 00
CCR1
RSCC
BRM
EDLX
EITS
ITF
XMFA
User’s Manual
Hardware Description
RSCC
7
RSC Interrupt for Cleared Channels
0 =
1 =
BOM Receive Mode - HDLC Channel 1
(significant in BOM mode only)
0 =
1 =
Enable DL-Bit Access through the Transmit FIFO - HDLC
Channel 1
A one in this bit position enables the internal DL-bit access through
the receive/transmit FIFO of the signaling controller. FMR1.EDL has
to be cleared.
Enable Internal Time Slot 0 to 31 Signaling - HDLC Channel 1
0 =
1 =
Interframe Time Fill - HDLC Channel 1
Determines the idle (= no data to be sent) state of the transmit data
coming from the signaling controller.
0 =
1 =
Transmit Multiframe Aligned - HDLC Channel 1
Determines the synchronization between the framer and the
corresponding signaling controller.
0 =
1 =
BRM
H
10-byte packets
Continuous reception
Continuous logical 1 is output
Continuous flag sequences are output (01111110 bit patterns)
RSC interrupt is generated for all channels.
RSC interrupt is generated only for those channels, that are
not cleared.
Internal signaling in time slots 0 to 31 defined by registers
RTR(4:1) or TTR(4:1) is disabled.
Internal signaling in time slots 0 to 31 defined by registers
RTR(4:1) or TTR(4:1) is enabled.
The contents of the XFIFO is transmitted without multiframe
alignment.
The contents of the XFIFO is transmitted multiframe aligned.
If CCR1.EDLXis set, transmission of DL-bits is started in F72
EDLX
EITS
353
ITF
XMFA
RFT1
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
RFT0
0
FALC
(09)
®
56