pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 74

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

4.1.13
The following functions are performed:
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If programmed and applicable to the selected multiframe format, CRC checking of the
incoming data stream is done by generating check bits for a CRC submultiframe
according to the CRC4 procedure (as defined in ITU-T G.704). These bits are compared
with those check bits that are received during the next CRC submultiframe. If there is at
least one mismatch, the 16-bit CRC error counter is incremented.
4.1.14
The received bit stream is stored in the receive elastic buffer. The memory is organized
as a two-frame elastic buffer with a maximum size of 64 × 8 bit. The size of the elastic
buffer can be configured independently for the receive and transmit direction.
Programming of the receive buffer size is done by SIC1.RBS1/0:
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The buffer functions are:
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User’s Manual
Hardware Description
Synchronization on pulse frame and multiframe
Error indication when synchronization is lost. In this case, AIS is sent automatically
to the system side and remote alarm is sent to the remote end if enabled.
Initiating and controlling of resynchronization after reaching the asynchronous state.
This can be done automatically by the FALC
microprocessor interface.
Detection of remote alarm indication from the incoming data stream.
Separation of service bits and data link bits. This information is stored in status
registers.
Generation of various maskable interrupt statuses of the receiver functions.
Generation of control signals to synchronize the CRC checker, and the receive
elastic buffer.
RBS1/0 = 00: two frame buffer or 512 bits
Maximum of wander amplitude (peak-to-peak): 190 UI (1 UI = 488 ns)
average delay after performing a slip: 1 frame or 256 bits
RBS1/0 = 01: one frame buffer or 256 bits
Maximum of wander amplitude: 100 UI
average delay after performing a slip: 128 bits, (SYPR = output)
RBS1/0 = 10: short buffer or 96 bits
Maximum of wander amplitude: 38 UI
average delay after performing a slip: 48 bits, (SYPR = output)
RBS1/0 = 11: Bypass of the receive elastic buffer
Clock adaption between system clock (SCLKR) and internally generated route clock
(RCLK).
Compensation of input wander and jitter.
Frame alignment between system frame and receive route frame
Framer/Synchronizer (E1)
Receive Elastic Buffer (E1)
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Functional Description E1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
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