pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 200
pef2256e
Manufacturer Part Number
pef2256e
Description
E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF2256E.pdf
(518 pages)
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Table 50
Register Setting
FMR2.FRS(2:1) = 10
FMR1.AFR = 1
FMR2.ALMF = 1
FMR2.FRS1/0 = 11
Table 51
Register Setting
MODE = 88
MODE2= 88
MODE3= 88
CCR1 = 18
CCR3= 08
CCR4= 08
User’s Manual
Hardware Description
H
H
H
H
H
H
Framer Initialization (E1) (cont’d)
HDLC Controller Initialization (E1)
Function
In this mode a search of double framing is automatically
restarted, if no CRC4 multiframing is found within 8ms. Together
with FMR2.AXRA = 1 this mode is essential to meet ETS300
011 and reduces the processor load heavily.
The receiver initiates a new basic- and multiframing research if
more than 914 CRC4 errors have been detected in one second.
In the interworking mode the FALC
format if no multiframe pattern is found in a time interval of
400 ms. This is also indicated by a 400 ms interrupt. Additionally
the extended interworking mode (FMR3.EXTIW = 1) will activate
after 400 ms the remote alarm (FMR2.AXRA = 1) and will still
search the multiframing without switching completely to the
double framing. A complete resynchronization in an 8 ms
interval is not initiated.
Function
HDLC channel 1, 2, and 3receivers active on line side, no
address comparison.
Enable signaling via TS(31:0), interframe time fill with
continuous flags (channel 1).
Interframe time fill with continuous flags (channel 2).
Interframe time fill with continuous flags (channel 3).
200
®
Operational Description E1
56 stays in double framing
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56
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