pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 315

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

CRC Error Counter 2 (Read)
CEC2L
CEC2H
CC(15:0)
User’s Manual
Hardware Description
CC15
CC7
7
7
CRC Error Counter (reported from TE through S
Depending on bit LCR1.EPRM the error counter increment is
selected:
LCR1.EPRM = 0:
If doubleframe format is selected, CEC2H/L has no function. If
CRC-multiframe mode is enabled, CEC2H/L works as S
indication counter (16 bits) which counts the S
and 0011in every received CRC submultiframe.
Incrementing the counter is only possible in the multiframe
synchronous state FRS0.LMFA = 0.
S
SA61 is received in frame 1 or 9 in every multiframe.
During alarm simulation, the counter is incremented once per
submultiframe up to its saturation.
Pseudo-Random Binary Sequence Error Counter
LCR1.EPRM = 1:
This 16-bit counter is incremented with every received PRBS bit error
in the PRBS synchronous state RSP.LLBAD = 1. The error counter
does not roll over.
During alarm simulation, the counter is incremented continuously with
every second received bit.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCEC2
has to be set. With the rising edge of this bit updating of the buffer is
stopped and the error counter is reset. Bit DEC.DCEC2 is reset
automatically with reading the error counter high byte.
a
6-bit sequence: SA61, SA62, SA63, SA64 = 0001 or 0011 where
315
a
6-bit sequence 0001
a
DS1.1, 2003-10-23
6 -Bit)
PEF 2256 H/E
CC0
CC8
E1 Registers
0
0
a
FALC
6-bit error
(58)
(59)
®
56