pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 198

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 48
Configuration
System clocking and data rate
Transmit offset counters
Receive offset counters
AIS to system interface
Operational Set Up
Select framing
Framing additions
Synchronization mode
Signaling mode
Features like channel loop-back, idle channel activation, extensions for signaling
support, alarm simulation, etc. are activated later. Transmission of alarms (e.g. AIS,
remote alarm) and control of synchronization in connection with consequent actions to
remote end and internal system depend on the activation procedure selected.
Note: Read access to unused register addresses: value should be ignored.
User’s Manual
Hardware Description
Write access to unused register addresses: should be avoided, or set to 00
address range up to AF
defined elsewhere.
All control registers (except XFIFO, XS(16:1), CMDR, DEC) are of type Read/
Write.
Initialization Parameters (E1) (cont’d)
H
; must be avoided in address range above AF
198
Register Setting
SIC1.SSCC(1:0),
SIC1.SSD1,FMR1.SSD0
CMR2.IRSP/IRSC/IXSP/IXSC
XC0.XCO, XC1.XTO
RC0.RCO, RC1.RTO
FMR2.DAIS/SAIS
FMR2.RFS(1:0), FMR1.XFS
RC1.ASY4, RC1.SWD
FMR1.AFR, FMR2.ALMF
XSP, XSW, FMR1.ENSA, XSA(8:4),
TSWM, MODE, CCR1, CCR2, RAH(2:1),
RAL(2:1)
Operational Description E1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
H
if not
®
H
56
in