pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 372

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Transmit Control 1 (Read/Write)
Value after reset: 9C
XC1
XCO(7:0)
User’s Manual
Hardware Description
XCO7
7
A write access to this address resets the transmit elastic buffer to its
basic starting position. Therefore, updating the value should only be
done when the FALC
centered. As a consequence a transmit slip will occur.
Transmit Offset
Initial value loaded into the transmit bit counter at the trigger edge of
SCLKX when the synchronous pulse on port SYPX/XMFS is active.
Calculation of delay time T (SCLKX cycles) depends on the value X
of the transmit offset register XC(1:0):
system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)
0 ≤T ≤4: X = 4 - T
5 ≤T ≤maximum delay: X = 256 × SC/SD - T + 4)
with maximum delay = (256 × SC/SD) -1
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
with SD = 2.048 Mbit/s (system clocking n × 2.048 MHz)
or
system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)
0 ≤T ≤4: X = 3 - T + 7 × SC/BF
5 ≤T ≤maximum delay: X = 200 × SC/BF - T + 3
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
SD = 1.544 Mbit/s (system clocking n × 1.544 MHz)
with BF = basic frequency = 1.544 MHz
T = Time between the active edge of SCLKX after SYPX pulse begin
and beginning of the next frame (F-bit, channel phase 0), measured
in number of SCLKX clock intervals; maximum delay:
T
See
max
H
page 185
= (200 × SC/BF) - (7 × SC/BF) - 1
for further description.
®
56 is initialized or when the buffer should be
372
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
XCO0
0
FALC
(23)
®
56