tmp86fp24 TOSHIBA Semiconductor CORPORATION, tmp86fp24 Datasheet
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tmp86fp24 Summary of contents
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... Bit Microcontroller TLCS-870/C Series TMP86FP24 ...
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The information contained herein is subject to change without notice. 021023_D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and ...
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... The TMP86FP24 is the high-speed, high-performance and low-power consumption 8-bit microcomputer, including ROM, RAM, LCD driver, multi-function timer/counter, serial interface (UART, HSIO), a 10-bit AD converter and two clock generators on chip. The TMP86FP24 has bytes BOOT ROM (masked ROM) for programming to flash memory. ...
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... SLEEP1 mode: CPU stops, and peripherals operate using low-frequency clock. x Release by interrupts. SLEEP2 mode: CPU stops, and peripherals operate using high and low frequency clock. x Release by interrupts. Wide operating voltage: 1 MHz/32.768 kHz i 2 MHz/32.768 kHz 86FP24-2 TMP86FP24 2007-08-24 ...
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... TMP86FP24 P47 (SEG16) P46 (SEG17) P45 (SEG18) P44 (SEG19) P43 (SEG20) P42 (SEG21) P41 (SEG22) P40 (SEG23/STOP4) P53 P52 P51 ( ) DVO P50 ( ) PPG P67 (AIN7/STOP3) P66 (AIN6/STOP2) P65 (AIN5/STOP1) P64 (AIN4/STOP0) ...
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... TC1 TC2 Watchdog timer P6 P1 10-bit AD converter AVDD P67 (AIN7) P15 to P10 to VAREF P60 (AIN0) Analog reference pins 86FP24-4 TMP86FP24 P47 (SEG16) I/O port to P40 (SEG23) P37 to P30 P4 P3 BOOT ROM (Flash) (mask ROM) 8-bit HSIO timer/counter UART TC3 TC5 SIO2 ...
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... Pin Funtions The TMP86FP24 has MCU mode and serial PROM mode. (1) MCU mode Make sure to fix the TEST pin to low level. (2) Serial PROM mode In the serial PROM mode, programming to flash memory is available by executing BOOT ROM. For details, refer to 2.16 “Serial PROM Mode”. ...
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... When used as an input port, respective output control Divider output (P5OUTCR) should be cleared to “0” after setting output latch (P5DR) to “1”. When used as a PPG output or divider PPG output output, respective P5DR should be set to “1”. 86FP24-6 TMP86FP24 2007-08-24 ...
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... Resonator connecting pins for high-frequency clock. For inputting external clock, XIN is used and XOUT is opened. Reset signal input Test pin for out-going test. Be fixed to low. Power supply for operation Analog reference voltage for AD conversion AD circuit power supply 86FP24-7 TMP86FP24 AD converter analog inputs 2007-08-24 ...
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... FFB0H FFBFH FFC0H FFDFH FFE0H FFFFH Figure 1.1.1 Memory Address Maps 1.2 Program Memory (ROM) The TMP86FP24 has bits (Address 4000H to FFFFH) of program memory (FLASH). 64 bytes ROM: FLASH memory includes: Vector table BOOT ROM: FLASH writing program 2048 bytes RAM: Random access memory includes: ...
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... Data Memory (RAM) The TMP86FP24 has 2048 bytes of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example: Clears RAM to “ ...
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... Timing generator control register TBTCR 0036H fc Timing generator fs System clocks Clock generator control Low-frequency clock XOUT XTIN XTOUT (Open) (c) Crystal 86FP24-10 TMP86FP24 Standby controller 0038H 0039H SYSCR1 SYSCR2 System control registers XTIN XTOUT (Open) (d) External oscillator 2007-08-24 ...
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... Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW mode. In SLOW and SLEEP mode, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. 86FP24-14 TMP86FP24 2007-08-24 ...
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... Note 2: When the STOP mode is started with the EEPCR<MNPWDW> “1”, the CPU wait period for stablizing of the power supply of flash control circuit is executed after the STOP warm-up time. 86FP24-15 “1”, EF7 (TBT interrupt individual “1”, interrupt processing is performed. and SLEEP0/1/2 modes are started TMP86FP24 “1”, the INTTBT with the 2007-08-24 ...
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... Reset Reset Operate Operate Halt Halt Operate with high frequency Halt Operate with low frequency Operate Halt Operate with low frequency Halt Halt 86FP24-16 TMP86FP24 RESET “1” “1” STOP “1” Other Machine Peripherals Cycle Time Reset 4/fc [s] Operate Halt 4/fc [s] ...
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... CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2, SLEEP1/2 mode) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0, SLEEP0 mode) “1”. 86FP24-17 TMP86FP24 (Initial value: 0000 00**) R/W Return to SLOW mode /fs ...
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... STOP STOP pin input is high, executing an instruction which starts STOP ( INT5 INT5 86FP24-18 TMP86FP24 pin input and STOP (External interrupt input “1”, the CPU wait pin must be used for pin high or setting STOP pin input is low. The ...
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... STOP mode is not “0”) pin. In the edge-sensitive STOP STOP (SYSCR1), 10010000B ; Starts after specified to the edge-sensitive release mode. 86FP24-19 TMP86FP24 pin input goes low STOP NORMAL operation pin STOP pin STOP pin input. ...
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... STOP mode is released by the hardware at the rising edge of pin input. STOP “1”, the CPU wait for the power supply of flash pin input must also be “H” level, rising RESET RESET 86FP24-20 TMP86FP24 STOP operation pin, RESET pin input voltage will pin RESET 2007-08-24 ...
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... Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered an approximate value. Note 2: The CPU wait period for FLASH is shown in parentheses. 86FP24-21 TMP86FP24 16.0 MHz, fs 32.768 kHz) Return to SLOW Mode 750 (0 ...
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... Figure 1.4.10 STOP Mode Start/Release (when EEPCR<MNPWDW> 86FP24-22 TMP86FP24 “0”) 2007-08-24 ...
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... Figure 1.4.11 STOP Mode Start/Release (when EEPCR<MNPWDW> 86FP24-23 TMP86FP24 “1”) 2007-08-24 ...
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... Therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until the CPU wait is finished. Figure 1.4.12 IDLE1/2, SLEEP1/2 Modes by instruction Yes Reset Reset input No Yes “0” CPU wait IMF “1” (Interrupt release mode) 86FP24-24 TMP86FP24 2007-08-24 ...
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... Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. 86FP24-25 SLEEP1/2 modes are started /fc [s] and that of SLEEP1/2 10 “1”) TMP86FP24 with the 2007-08-24 ...
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... Figure 1.4.13 IDLE1/2, SLEEP1/2 Modes Start/Release 86FP24-26 TMP86FP24 2007-08-24 ...
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... Note 2: During CPU wait, though CPU operations “1” remain halted, but the peripheral function operation is resumed. Therefore in this enable time, though the interrupt latch might be Yes set, interrupt operation is not executed until the CPU wait is finished. IMF “1” (Interrupt release mode) TMP86FP24 2007-08-24 ...
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... IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR<TBTCK>. Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/ SLEEP0 mode is started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be started. 86FP24-28 TMP86FP24 /fs [s]. 3 modes start/release without reference “ ...
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... Figure 1.4.15 IDLE0, SLEEP0 Modes Start/Release 86FP24-29 TMP86FP24 2007-08-24 ...
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... PINTTC2: CLR (TC2CR). 5 SET (SYSCR2). 5 CLR (SYSCR2). 7 RETI VINTTC2: DW PINTTC2 86FP24-30 TMP86FP24 ; SYSCR2<SYSCK> (Switches the main system clock to the low-frequency clock for SLOW2.) ; SYSCR2<XEN> (Turns off high-frequency oscillation.) ; SYSCR2<XTEN> Sets mode for TC2 ; Sets warm-up time (Depend on oscillator accompanied.) ...
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... Low-frequency clock Main system clock SYSCK Note 2: SLOW mode can also be released by inputting low level on the which immediately performs the reset operation. After reset, the TMP86FP24 is placed in NORMAL1 mode. Example: Switching from the SLOW1 mode to the NORMAL2 mode. (fc 16 MHz, warm-up time is 4 ...
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... Figure 1.4.16 Switching between the NORMAL2 and SLOW Modes 86FP24-32 TMP86FP24 2007-08-24 ...
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... Interrupt Control Circuit The TMP86FP24 has a total (Reset is excluded interrupt source: 5 externals and 14 internals the internal sources are non-maskable interrupts, and the rest of them are maskable interrupts. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to “ ...
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... Figure 1.5.1 Interrupt Controller Block Diagram 86FP24-34 TMP86FP24 2007-08-24 ...
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... IMF m 0 (ILE), 11110011B ; (ILL), 1110100000111111B ; IMF m 1 WA, (ILL (IL). then jump SSET 003AH and 003BH in SFR , “0”, all maskable interrupts are not accepted 86FP24-35 TMP86FP24 2007-08-24 ...
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... are located on EIRE, EIRL to EIRH IMF m “0” “1” Note: IMF is not set. ; IMF m “1” 3AH shows EIRL address */ TMP86FP24 are 4 m “1” 5 2007-08-24 ...
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... Disable the acceptance of each maskable interrupt. 1: Enable the acceptance of each maskable interrupt. 0: Disable the acceptance of all maskable interrupts. 1: Enable the acceptance of all maskable interrupts. 86FP24-37 TMP86FP24 ILL (003CH) (Initial value: 00000000 000000**) ...
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... Figure 1.5.3 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Interrupt service task Execute Interrupt acceptance instruction 86FP24-38 TMP86FP24 Execute RETI instruction 2007-08-24 ...
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... At execution of interrupt PUSH instruction Entry address D203H Vector D204H WA ; Save WA register Restore WA register. ; RETURN SP PCL PCH PSW SP At execution of POP At execution instruction of an RETI instruction 86FP24-39 TMP86FP24 Interrupt service 0FH program 06H Address (Example) 023AH 023B 023C 023D 023E 023F 2007-08-24 ...
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... PCL and PCH are located on address ( and ( respectively. Note: If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again. ; Save A register. ; Restore A register. ; RETURN Interrupt service task Saving registers Restoring registers 86FP24-40 TMP86FP24 2007-08-24 ...
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... Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 86FP24-41 TMP86FP24 ; Recover ...
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... External Interrupts The TMP86FP24 has five external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT3. ...
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... Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P00 input/output port 1: pin (Port P00 should be set to an input mode) INT 0 0: Rising edge 1: Falling edge 86FP24-43 TMP86FP24 Digital Noise Reject 0) is not set /fc (Initial value: 00** 000*) R/W 2007-08-24 ...
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... Reset Circuit The TMP86FP24 has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Since the reset circuit has an 11-stage counter for generation of flash reset, which is the reset counter for stabilizing of the power supply for flash, the reset period ...
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... In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”. x When the system clock reset is generated, the flash reset is also generated. Therefore, the maximum reset period is 24/fc [ Reset release 10 4/fc to 12/fc [s] 16/fc [s] 2 /fc [s] for Flash reset “1”) space. /fc [s] (65 16.0 MHz). 10 86FP24-45 TMP86FP24 Instruction at address r 2007-08-24 ...
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... On-chip Peripherals Functions 2.1 Special Function Register (SFR) The TMP86FP24 adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 1F80H to 1FFFH. Figure 2.1.1 to Figure 2.1.2 indicate the special function register (SFR) and data buffer register (DBR) for TMP86FP24 ...
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... Note 1: Do not access reserved areas by the program. Note 2: : Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Figure 2.1.2 The Special Function Register (SFR) for TMP86FP24 (2/2) Address Read Bit2 ...
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... I/O Ports The TMP86FP24 has 8 parallel input/output ports (54 pins) as follows. Primary Function Port P0 8-bit I/O port Port P1 6-bit I/O port Port P2 4-bit I/O port Port P3 8-bit I/O port Port P4 8-bit I/O port Port P5 4-bit I/O port Port P6 8-bit I/O port Port P9 8-bit I/O port Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing ...
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... Read only Output latch P03 P02 P01 P00 TC2 INT2 INT1 INT0 0: Sink open-drain output 1: CMOS output P03 P02 P01 P00 Figure 2.2.2 Port 0 86FP24-49 TMP86FP24 P0i Note (Initial value: 1111 1111) (Initial value: 0000 0000) R/W 2007-08-24 ...
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... P13 P12 P11 P10 TC5 SI2 SO2 SCK2 PWM5 PDO5 0: Sink open-drain output 1: CMOS output P13 P12 P11 P10 Figure 2.2.3 Port 1 86FP24-50 TMP86FP24 P1i Note (Initial value: **11 1111) *: Don’t care (Initial value: **00 0000) *: Don’t care R/W 2007-08-24 ...
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... For details, refer to 2.8 “8-Bit Timer/Counter 3” read instruction is executed for TC3SEL, read data of bits are unstable. TC3SEL (0029H) TC3INV TC3 input control Figure 2.2.4 TC3 Input Control TC3INV (Initial value: **** ***0) *: Don’t care 0: Normal input 1: Inverted input 86FP24-51 TMP86FP24 R/W 2007-08-24 ...
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... Data output (P22 Output latch P2OUTCR D Q P2OUTCR input fs STOP OUTEN XTEN Note: When XTEN<SYSCR2> is set to “1”, P21 and P22 become a high impedance state. Figure 2.2.5 Port 2 (P21 and P22) Osc.enable 86FP24-52 TMP86FP24 VDD P21 (XTIN) VDD P22 (XTOUT) 2007-08-24 ...
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... XTIN INT5 STOP 0: Sink open-drain output 1: CMOS output (P20, P23 ports) CMOS output with pull-up resistor (P21, P22 ports) P23 P22 P21 P20 86FP24-53 TMP86FP24 P20 ( , ) INT5 STOP P23 (Initial value: **** 1111) *: Don’t care (Initial value: **** 0000) *: Don’t care ...
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... P36 P35 P34 Read only Output latch P33 P32 P31 P30 0: Sink open-drain output 1: CMOS output P33 P32 P31 P30 Figure 2.2.7 Port 3 86FP24-54 TMP86FP24 P3i Note (Initial value: 1111 1111) (Initial value: 0000 0000) R/W 2007-08-24 ...
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... P4PRD read 0 0 Terminal input 0 1 Terminal input 1 0 Terminal input 1 1 Terminal input * * “0” “0” 86FP24-55 TMP86FP24 Output Remark Low I/O High-Z I/O Low I/O (Pull down) Low I/O (Pull down) Low LCD Blanking Segment LCD High-Z Key-on wakeup Output Remark Low ...
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... STOP4 0: P4 input/output port 1: LCD segment output 0: Pull-down disable 1: Pull-down enable P43 P42 P41 P40 Figure 2.2.8 Port 4 86FP24-56 TMP86FP24 P40 Note: STOP4EN is bit4 in STOPCR. P4i Note (Initial value: 1111 1111) (Initial value: 0000 0000) R/W (Initial value: 0000 0000) R/W 2007-08-24 ...
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... Data input (P5PRD) Data input (P5DR) Data output (P5DR) Control output P5DR (0005H) R Output latch P53 P52 P51 P50 (Initial value: **** 1111) DVO PPG *: Don’t care Figure 2.2.9 Port 5 86FP24-57 TMP86FP24 P5i Note 2007-08-24 ...
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... P5OUTCR (000DH) Port P5 output circuit control P5OUTCR (Set for each bit individually) P5PRD (1FF2H) Read only Figure 2.2.10 P5OUTCR and P5PRD (Initial value: **** 0000) *: Don’t care 0: Sink open-drain output 1: CMOS output P53 P52 P51 P50 86FP24-58 TMP86FP24 R/W 2007-08-24 ...
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... Low 1 “1” (Output latch) High Terminal input High-Z * P6i Note Note 2: SAIN is bit0 to bit3 in ADCCR1 Q 86FP24-59 TMP86FP24 Remark Input mode Output mode Output mode Remark Input mode Output mode Output mode Key-on wakeup 2007-08-24 ...
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... Note 2: SAIN is bit0 to bit3 in ADCCR1 Q Note 3: STOPkEN is bit7 to bit4 in STOPCR P63 P62 P61 P60 AIN3 AIN2 AIN1 AIN0 (Initial value: 0000 0000) (Initial value: 0000 0000) 0: Input mode or analog input 1: Output mode (Initial value: 1111 1111) 0: Input disable 1: Input enable 86FP24-60 TMP86FP24 R/W R/W 2007-08-24 ...
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... Terminal input 0 1 Terminal input 1 0 Terminal input 1 1 Terminal input * * “0” “0” Figure 2.2.13 Port 9 86FP24-61 TMP86FP24 Output Remark Low I/O High-Z I/O Low I/O (Pull down) Low I/O (Pull down) Low LCD Blanking Segment LCD P9i Note 2007-08-24 ...
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... Figure 2.2.14 P9DR, P9LCR, P9PDCR and P9PRD P93 P92 P91 P90 (Initial value: 1111 1111) SEG12 SEG13 SEG14 SEG15 (Initial value: 0000 0000 input/output port 1: LCD segment output (Initial value: 0000 0000) 0: Pull-down disable 1: Pull-down enable P93 P92 P91 P90 86FP24-62 TMP86FP24 R/W R/W 2007-08-24 ...
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... Pin WAKE The TMP86FP24 has the function of outputting a monitor signal to the outside upon release of STOP mode by an external interrupt signal input. This pin is assigned as the dedicated output pin and it has N-ch open-drain form. This function enables the real time notification of the start/release of STOP mode timing to the outside. Therefore effective for the system which requires the stop control against a peripheral device connected to the microcontroller ...
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... Example: Sets the time-base-timer frequency to fc SET Falling edge detector TBTEN (a) Configuration Interrupt period (b) Time-base-timer interrupt Figure 2.3.1 Time-base-timer 16 [Hz] and enables an INTTBT interrupt. (TBTCR), 00000010B ; TBTCK m 010 (TBTCR), 00001010B ; TBTEN IMF m (EIRL), 6 86FP24-64 TMP86FP24 IDLE0/SLEEP0 release request INTTBT interrupt request MPX: Multiplexer 2007-08-24 ...
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... MHz, fs Time-base-timer Interrupt Frequency [Hz] NORMAL1/2, IDLE1/2 Modes SLOW, SLEEP 0 DV7CK 1 1.91 1 7.63 4 244.14 128 976.56 512 1953.13 1024 3906.25 2048 7812.5 4096 16384 86FP24-65 TMP86FP24 (Initial value: 0000 0000) SLOW, SLEEP Mode 1 15 fs/2 13 fs/2 R 32.768 kHz) Modes 2007-08-24 ...
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... Writing disable WDTT WDTEN code 0034H WDTCR1 Watchdog timer control registers Figure 2.4.1 Watchdog Timer Configuration Reset release signal from TG Overflow WDT output 1 2 Writing clear WDTOUT code Controller 0035H WDTCR2 86FP24-66 TMP86FP24 Reset request Interrupt request INTWDT MPX: Multiplexer 2007-08-24 ...
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... Clears the binary counters. (WDTCR1), 00001101B ; WDTT m 10, WDTOUT m 1 (WDTCR2), 4EH ; Clears the binary counters. (Always clear immediately before and after changing WDTT.) (WDTCR2), 4EH ; Clears the binary counters. (WDTCR2), 4EH ; Clears the binary counters. 86FP24-67 TMP86FP24 At this time, when 2007-08-24 ...
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... Reset request Watchdog timer binary counter clear (Clear code Watchdog timer disable (Disable code Enable assigning address trap area H Others: Invalid 86FP24-68 TMP86FP24 (Initial value: **11 1001) SLOW mode DV7CK Write 2 / only 2 /fs 2 /fs ...
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... MHz, fs Watchdog Timer Detection Time [s] NORMAL1/2 Mode SLOW Mode 0 DV7CK 250 m 250 m 62.5 m 62.5 m SP, 023FH ; Sets the stack pointer. (WDTCR1), 00001000B ; WDTOUT / 86FP24-69 TMP86FP24 32.768 kHz) /fc [s] (65 (WDTT Reset generate 2007-08-24 ...
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... Reset request D2H: Address trapped area valid to set (ATRAP control code) 4EH: Watchdog timer binary counter clear (WDT clear code) B1H: Watchdog timer disable(WDT disable code) Others: Invalid 86FP24-70 TMP86FP24 (Initial value: **11 1001) Write only (Initial value: **** ****) Write only 2007-08-24 ...
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... P51 ( ) DVO P51 output latch DVOEN pin output DVO (b) Timing Chart Figure 2.5.2 Divider Output 86FP24-71 TMP86FP24 ). The P51 output latch DVO (Initial value: 0000 0000) SLOW, SLEEP Mode 1 R fs/2 fs fs/2 fs fs/2 fs/2 ...
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... Timer/Counter 1 2.6.1 Configuration Figure 2.6.1 Timer/Counter 1 (TC1) 86FP24-72 TMP86FP24 2007-08-24 ...
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... External trigger start at the falling edge u 0: Auto-capture disable 1: Auto-capture enable 0: Double edge capture 1: Single edge capture 0: Trigger start 1: Trigger start and stop 0: Continuous pulse generation 1: One shot 0: Clear 1: Set 86FP24-73 TMP86FP24 TC1DRAL (0020H) TC1DRBL (0022H) SLOW1/2, SLEEP1/2 mode 3 fs/2 ...
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... Enable INTTC1. IMF (TC1CR), 00000000B TFF1 m “0”, TC1CK m “00”, TC1M m “00” (TC1CR), 00010000B Starts TC1. (TC1CR), 01010000B ACAP1 m “1” (Capture) WA, (TC1DRB) Reads the capture value. 86FP24-74 TMP86FP24 16 MHz, fs 32.768kHz) SLOW1/2, SLEEP1/2 Modes Maximum Resolution Time Setting [Ps] [s] 244.14 16.0 ...
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... Source clock Up counter TC1DRB ? ACAP1 Figure 2.6.3 Timer Mode Timing Chart Match detect Counter clear (a) Timer mode Capture (b) Auto capture 86FP24-75 TMP86FP24 Capture 2007-08-24 ...
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... TC1 external trigger start, METT1 ; IMF “0” /fc 1F40H ; INTTC1 interrupt enable. ; IMF “1” ; TFF1 “0”, TC1CK ; TC1 external trigger start, METT1 TMP86FP24 “10”, TC1M “00” “0” “10”, TC1M “00” 1 2007-08-24 ...
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... Trigger Trigger Match detect (b) Trigger start and Stop (METT1 Match detect Counter clear 86FP24-77 TMP86FP24 Count start TC1S 10 at Trigger the rising edge TC1S 10 at the rising edge Note: m < Counter clear ...
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... SLOW1/2, SLEEP1/2 Modes / /fc 2 /fs Count stop Count start Match detect (a) Positive logic (at TC1S 10) Count stop (b) Negative logic (at TC1S 11) 86FP24-78 TMP86FP24 Counter clear Count start Match detect Counter clear 2007-08-24 ...
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... INTTC1 service switch initial setting. ; Sets the TC1 mode and source clock. ; IMF “0” ; Enables INTTC1. ; IMF “1” ; Starts TC1 with an external trigger at MCAP1 0. ; Inverts INTTC1 service switch. ; Reads TC1DRB (“H” level pulse width). ; Reads TC1DRB (Period). ; Duty calculation. WIDTH TMP86FP24 2007-08-24 ...
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... Single edge capture (MCAP1 “1” Capture n [Application] (1) Period/frequency measurement (2) Duty measurement (b) Double edge capture (MCAP1 “0”) 86FP24-80 TMP86FP24 Count start (TC1S “10” Count start (TC1S “10” Capture ...
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... Example: Pulse output “H” level 800 Ps, “L” level 200 Ps (at fc SET (P5DR (TC1CR), 10001011B LDW (TC1DRA), 07D0H LDW (TC1DRB), 0190H LD (TC1CR), 10011011B 86FP24-81 TMP86FP24 ) pin holds the same level that it does just PPG 16 MHz, DV7CK 0). ; P50 output latch Sets the PPG output mode Sets the period ( /fc ...
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... TC1S clear Figure 2.6.8 Output PPG (a) Continuous pulse generation (with TC1S [Application] One shot pulse output (b) One shot (with TC1S 10) 86FP24-82 TMP86FP24 P50 ( ) pin PPG MPX: Multiplexer Note: m > n 01) Note: m > n 2007-08-24 ...
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... Note 2: When control input/output is used, I/O port setting should be set correctly. For details, refer to 2.2 “I/O ports”. Figure 2.7.1 Timer/Counter 2 (TC2A TC2S Source Clear clock B 16-bit up counter TC2M CMP TC2DR 16-bit timer register 2 86FP24-83 TMP86FP24 Match INTTC2 interrupt Enable Match detect control TC2DRL TC2DRH write strobe write strobe 2007-08-24 ...
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... Reserved 111 External clock (TC2 pin input) 0: Stop and counter clear 1: Start 0). > warm up 86FP24-84 TMP86FP24 TC2DRL (0024H) SLOW1/2 SLEEP1/2 mode mode 15 15 fs/2 fs fs (Note 2007-08-24 ...
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... Ps 32. 62 (Note) 30. [Hz] and generates an interrupt every 25 ms (at fc LDW (TC2DR), 0C350H ; DI SET (EIRE (TC2CR), 00001100B ; LD (TC2CR), 00101100B ; 86FP24-85 TMP86FP24 16 MHz) SLEEP1/2 Mode Maximum Maximum Resolution Time Setting 18.20 h 1.00 s 18.20 h 1.07 min 0.98 ms 1.07 min 3 Sets TC2DR ( /fc C350H). IMF “0” ...
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... Table 2.7.2 Timer/Counter 2 External Clock Source Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 Modes 3 “H” Width 2 /fc 3 “L” Width 2 /fc 86FP24-86 TMP86FP24 ; Sets TC2DR. ; IMF “0” ; Enables INTTC2 interrupt. ; IMF “1” ; TC2CK m “111”, TC2M m “0” ...
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... SET (EIRE (TC2CR), 00000101B ; LD (TC2CR), 00100101B ; Match detect 86FP24-87 TMP86FP24 13 Sets TC2DR (120 /fc 00EAH). IMF “0” Enables INTTC2 interrupt. IMF “1” TC2CK m “001”, TC1M m “1” Starts TC2 Counter clear ...
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... Note 2: When control input/output is used, I/O port setting should be set correctly. For details, refer to 2.2 “I/O ports”. Figure 2.8.1 Timer/Counter 3 (TC3) TC3S Clear Edge detector Falling Rising Source clock 8-bit up counter CMP Capture TC3DRB TC3DRA 8-bit timer register 3A, B ACAP 86FP24-88 TMP86FP24 Overflow INTTC3 S interrupt Match TC3S Capture 2007-08-24 ...
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... DV7CK 0 DV7CK 13 000 fc/2 12 001 fc/2 11 010 fc/2 10 011 fc/2 9 100 fc/2 8 101 fc/2 7 110 fc/2 111 External clock (TC3 pin input) 0: Stop and clear 1: Start Auto-capture enable 0 TC3INV 0: Normal 1: Invert 86FP24-89 TMP86FP24 SLOW1/2, SLEEP1/2 Mode fs/2 fs fs/2 fs fs/2 fs fs/2 fs/2 R/W fs/2 fs fc/2 (Initial value: **** ***0) R/W 2007-08-24 ...
Page 92
... SLOW1/2 Modes DV7CK 1 Resolution Maximum Resolution Time Setting [Ps] [Ps] [ms] 976.6 249.0 976.6 488.3 124.5 488.3 244.1 62.3 244.1 122.0 31.1 122.0 61.0 15.6 61.0 16.0 4.1 8.0 2.0 86FP24-90 TMP86FP24 16 MHz) Maximum Time Setting [ms] 249.0 124.5 62.3 31.1 15 2007-08-24 ...
Page 93
... Table 2.8.2 Source Clock (External clock) for Timer/Counter Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 Modes 2 “H” Width 2 /fc 2 “L” Width 2 /fc 86FP24-91 TMP86FP24 “1”, the detection of match is executed at the SLOW1/2, SLEEP1/2 Modes /fs 2007-08-24 “1”, the ...
Page 94
... After generating of interrupt, the capture function and overflow detection stop until the TC3DRA is read, but the counting is continued. Because the capture function and overflow detection are restarted by reading TC3DRA, read the TC3DRB before the reading TC3DRA. 86FP24-92 Capture into INTTC3 Interrupt TC3DRA Rising edge Falling edge TMP86FP24 2007-08-24 ...
Page 95
... Figure 2.8.3 Capture Mode Timing Chart 86FP24-93 TMP86FP24 2007-08-24 ...
Page 96
... Note 2: When control input/output is used, I/O port setting should be set correctly. For details, refer to 2.2 “I/O ports”. Figure 2.9.1 Timer/Counter 5 (TC5) Clear Overflow Match CMP PDO mode INTTC5 PWM interrupt output mode 86FP24-94 TMP86FP24 Timer F/F5 Toggle Port Clear / PWM5 (Note 2) PDO5 pin TC5S 2007-08-24 ...
Page 97
... TC5 operation is stopped (TC5S “1” o “1”), do not change TC5CR Event Counter Mode PDO Mode | 86FP24-95 TMP86FP24 SLOW1/2, SLEEP1/2 Modes “1” o “0”), do not PWM Mode ...
Page 98
... Table 2.9.2 Timer/Counter 5 External Clock Source “H” Width “L” Width SLOW1/2 Modes DV7CK 1 Resolution Maximum Resolution Time Setting [Ps] [Ps] [ms] 244.14 62.3 244.14 8.0 2.0 2.0 0.510 0.5 0.128 Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 Modes /fc 86FP24-96 TMP86FP24 16 MHz) Maximum Time Setting [ms] 62 2007-08-24 ...
Page 99
... Figure 2.9.3 PDO Mode Timing Chart 16 MHz). (TC5CR), 00000110B ; Sets PDO mode. (TC5M (P1DR P13 output latch m 1 (TC5DR), 3DH ; 1/1024 y 2 (TC5CR), 00100110B ; Starts TC5 86FP24-97 TMP86FP24 ) pin outputs an PDO5 10, TC5CK 001 3DH 2007-08-24 ...
Page 100
... Table 2.9.3 PWM Output Mode (Example TC5CK Resolution [ns] 000 001 010 011 500 100 250 101 125 110 ) pin outputs an inversion of the PWM5 n/m Overwrite 1 cycle 16 MHz) NORMAL1/2, IDLE1/2 Modes Repeat Cycle [Ps 128 62.5 86FP24-98 TMP86FP24 m/m Shift 2007-08-24 ...
Page 101
... UART (Asynchronous serial interface) The TMP86FP24 has 1 channel of UART (Asynchronous serial interface). The UART is connected to external devices via RXD and TXD. RXD is also used as P05; TXD, as P06. To use P05 or P06 as the RXD or TXD pin, set P0 port output latches to “1”. 2.10.1 Configuration ...
Page 102
... RXDNC STOPBR 0: 1 bit 1: 2 bits 00: No noise rejection (Hysteresis input) 01: Rejects pulses shorter than 31/fc [s] as noise 10: Rejects pulses shorter than 63/fc [s] as noise 11: Rejects pulses shorter than 127/fc [s] as noise 86FP24-100 TMP86FP24 Write only Write only 2007-08-24 ...
Page 103
... Receive data buffer empty 1: Receive data buffer full 0: No overrun error 1: Overrun error 0: No framing error 1: Framing error 0: No parity error 1: Parity error Read only (Initial value: 0000 0000 Write only (Initial value: 0000 0000) 86FP24-101 TMP86FP24 Read only 2007-08-24 ...
Page 104
... With parity/1 STOP bit Frame length Bit1 Bit6 Bit7 Stop 1 Bit1 Bit6 Bit7 Stop 1 Bit1 Bit6 Bit7 Parity Bit1 Bit6 Bit7 Parity Without parity/1 STOP bit Without parity/2 STOP bit With parity/2 STOP bit 86FP24-102 TMP86FP24 11 12 Stop 2 Stop 1 Stop 1 Stop 2 2007-08-24 ...
Page 105
... TC5 source clock TTREG5 set value Transfer clock 16 Bit0 Bit0 a) Without noise rejection circuit Bit0 Bit0 b) With noise rejection circuit Figure 2.10.4 Data Sampling 86FP24-103 TMP86FP24 4 MHz 19200 [baud] 9600 4800 2400 1200 600 2007-08-24 ...
Page 106
... Note: When a receive operation is disabled by setting UARTCR1<RXE> bit to “0”, the setting becomes valid when data receive is completed. However framing error occurs in data receive, the receive-disabling setting may not become valid framing error occurs, be sure to perform a re-receive operation. 86FP24-104 TMP86FP24 2007-08-24 ...
Page 107
... RDBUF is read after reading the UARTSR. Final bit RXD pin xxx0** Shift register UARTSR<FERR> INTRXD Figure 2.10.6 Generation of Framing Error Stop 1pxxxx0 pxxxx0* Reading UARTSR then RDBUF clears PERR. Stop 1xxxx0 xxxx0* Reading UARTSR then RDBUF clears FERR. 86FP24-105 TMP86FP24 2007-08-24 ...
Page 108
... UARTSR. RXD pin Final bit xxx0** Shift register yyyy RDBUF UARTSR<RBFL> INTRXD Figure 2.10.8 Generation of Receive Buffer Full Stop xxxx0* 1xxxx0 Reading UARTSR then RDBUF clears OERR. Stop xxxx0* 1xxxx0 xxxx 86FP24-106 TMP86FP24 Reading UARTSR then RDBUF clears RBFL. 2007-08-24 ...
Page 109
... TXD pin UARTSR<TBEP> UARTSR<TEND> INTTXD Figure 2.10.10 Generation of Transmit Buffer Empty y ****1x *1xxxx Bit0 Final bit *****1 Stop Data writing to TDBUF 86FP24-107 TMP86FP24 Data write zzzz 1yyyy0 *****1 Start Stop After reading UARTSR, writing TDBUF clears TBEP. 1yyyy0 *1yyyy Bit0 Start 2007-08-24 ...
Page 110
... Key-on wakeup (KWU) In the TMP86FP24, the STOP mode must be released by not only P20 ( also P64 to P67 and P40 pins. When the STOP mode is released by P40, P64 to P67 pins, the P20 ( be used. 2.11.1 Configuration Stop Mode Control INT5 Stop mode release signal (1: release) Figure 2 ...
Page 111
... Stop mode released by P66 port STOP3 Stop mode released by P67 port STOP4 Stop mode released by P40 port Figure 2.11.2 Key-on Wakeup Control Register 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 86FP24-109 TMP86FP24 (Initial value: 0000 0***) R/W 2007-08-24 ...
Page 112
... AD Converter (ADC) The TMP86FP24 has a 10-bit successive approximation type AD converter. 2.12.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 2.12.1. It consists of control registers ADCCR1 and ADCCR2, conversion result registers ADCDR1 and ADCDR2 converter, a sample-and-hold circuit, a comparator, and a successive comparison circuit. ...
Page 113
... AD conversion result register (ADCDR2) This register is used to store the digital value (Bit1 and bit0) after being converted by the AD converter, and then this register is also used to monitor the operating status of the AD converter. The AD converter control register configurations are shown in Figure 2.12.2 and Figure 2.12.3. 86FP24-111 TMP86FP24 2007-08-24 ...
Page 114
... 156 110 1248/fc 78 156 111 Reserved ) as follows. AREF 86FP24-112 TMP86FP24 (Initial value: 0001 0000) R/W (Initial value 0000 MHz 4 MHz 1 MHz 39 R 156 39 78 ...
Page 115
... EOCF is cleared the previous conversion result is retained until the next conversion is completed AD05 AD04 AD03 AD02 Before or during conversion 1: Conversion completed 0: During stop of AD conversion 1: During AD conversion 86FP24-113 TMP86FP24 (Initial value: 0000 0000) (Initial value: 0000 **** ) Read only 2007-08-24 ...
Page 116
... AD conversion ADCCR1<ADRS> start ADCDR2<ADBF> ADCDR1, 2 Indeterminate First conversion result ADCDR2<EOCF> INTADC request Reading ADCDR1 Reading ADCDR2 Figure 2.12.4 Operation in Software Start Mode AD conversion start Second conversion result Conversion Conversion result read result read 86FP24-114 TMP86FP24 2007-08-24 ...
Page 117
... A “11” Second conversion Third conversion Third conversion result Second conversion result First conversion result Conversion Conversion result read result read 86FP24-115 TMP86FP24 “00” AD conversion finished AD convert operation suspended. Conversion result is not stored. Conversion result read 2007-08-24 ...
Page 118
... The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 2.12.6. 3FFH 3FEH 3FDH 003H 002H 001H Analog input voltage Figure 2.12.6 Analog Input Voltage and AD Conversion Result (typ.) 1021 1022 1023 1024 86FP24-116 TMP86FP24 VAREF VASS u 1024 2007-08-24 ...
Page 119
... Toshiba also recommends attaching a capacitor external to the chip. AINi Allowable signal source impedance (max) Figure 2.12.7 Analog Input Equivalent Circuit and Example of Input Pin Processing Internal resistance Analog comparator (typ.) Internal capacitance (typ.) DA converter Note: i 86FP24-117 TMP86FP24 2007-08-24 ...
Page 120
... LCD Driver The TMP86FP24 has a driver and control circuit to directly drive the liquid crystal device (LCD). The pins to be connected to LCD are as follows: a. Segment output port b. Segment output or P4, P9 input/output port c. Common output port In addition, C0, C1, V1, V2, V3 pin are provided for the LCD driver’s booster circuit. ...
Page 121
... Duty (1/3 Bias) 01: 1/3 Duty (1/3 Bias) 10: 1/2 Duty (1/2 Bias) 11: Static NORMAL1/2,IDLE0/1/2 Modes SLOW1/2, SLEEP01/2 DV7CK 0 DV7CK 00: fc/2 fs 01: fc/2 fs 10: fc/2 fc 11: fc/2 fc should be satisfied should be satisfied 86FP24-119 TMP86FP24 Modes 5 fs/2 3 fs/2 2 fs/2 Reserved R/W Modes 9 fs/2 8 fs/2 Reserved Reserved 2007-08-24 ...
Page 122
... Duty (1/2 Bias Frame frequency LCD drive voltage LCD3 Figure 2.13.3 LCD Drive Waveform (COM-SEG pins) V LCD3 1 LCD3 Data “0” Data “1” (b) 1/3 Duty (1/3 Bias) V LCD3 1 LCD3 86FP24-120 TMP86FP24 F Data “0” Data “1” Data “0” (d) Static 2007-08-24 ...
Page 123
... Frame Frequency [Hz] 1/4 duty 1/3 duty 1/2 duty • • 128 171 86FP24-121 TMP86FP24 Static fc fc • 244 122 122 • 244 122 122 • 244 ...
Page 124
... Figure 2.13.5 Example of Divider Resistance (LCDCR<BRES> “0”) VDD Reference voltage (1V VSS Adjustment of contrast VDD Open C1 Open V1 R2 VSS 1/2 Bias (R1 R2) 86FP24-122 TMP86FP24 Reference C V1 voltage (2V Adjustment of contrast VDD Open C1 Open V1 R1 VSS Static 2007-08-24 ...
Page 125
... SEG0 SEG3 SEG2 SEG5 SEG4 SEG7 SEG6 SEG9 SEG8 SEG11 SEG10 SEG13 SEG12 SEG15 SEG14 SEG17 SEG16 SEG19 SEG18 SEG21 SEG20 SEG23 SEG22 Bit7/3 Bit6/2 Bit5/1 COM3 COM2 COM1 COM2 COM1 COM1 86FP24-123 TMP86FP24 Bit0 Bit4/0 COM0 COM0 COM0 COM0 2007-08-24 ...
Page 126
... Sets frame frquency (SLF) Sets P4, P9 port. Initialization of display data area. Display enable (EDSP) (Releases from blanking.) A, (80H) A, TABLE $ 7 HL, 1F80H W, ( (HL), W 11011111B, 00000110B, 11100011B, 10100111B, 00110110B, 10110101B, 11110101B, 00010111B, 11110111B, 10110111B 86FP24-124 TMP86FP24 16 [Hz]. LCD driving method, frame 2007-08-24 ...
Page 127
... COM0 COM1 COM2 COM3 SEG0 SEG1 Number Display 11011111 5 00000110 6 11100011 7 10100111 8 00110110 9 COM0 SEG0 SEG2 COM1 SEG1 Number High Order Address (1F81H) 5 **11**10 6 **11**11 7 **01**10 8 **11**11 9 **11**10 86FP24-125 TMP86FP24 Display Data 10110101 11110101 00000111 11110111 10110111 Display Data Low Order Address (1F80H) **01**01 **01**01 **00**11 **01**11 **01**11 2007-08-24 ...
Page 128
... LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 V LCD3 0 V LCD3 COM0 COM1 COM2 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 V LCD3 0 V LCD3 TMP86FP24 2007-08-24 ...
Page 129
... Figure 2.13.13 Static Drive 86FP24-127 COM0 COM1 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 V LCD3 0 V LCD3 COM0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 0 V LCD3 V LCD3 0 V LCD3 TMP86FP24 2007-08-24 ...
Page 130
... SIO (Synchronous serial interface) The TMP86FP24 contains two SIO (Synchronous serial interface) channel. They are connected to external devices via the SI1, SI2, SO1, SI2, pin is used also as the P05 (P11) pin, the SO1 (SO2) pin is used also as the P06(P10) pin, and the ( ) pin is used also as the P07 (P12) pin ...
Page 131
... LSB (Transfer beginning with bit0) NORMAL1/2, IDLE1/2 Mode DV7CK 0 DV7CK 13 000 fc/2 8 001 fc/2 6 010 fc/2 5 011 fc/2 4 100 fc/2 3 101 fc/2 2 110 fc/2 111 External clock (Supplied via the to “1” or setting SIO1CR1<SIOM>, 86FP24-129 TMP86FP24 R/W SLOW1/2, SLEEP1/2 1 Mode 5 5 fs/2 fs fc/2 pin) SCK1 SIO1CR1<SIODIR> or “0”). 2007-08-24 ...
Page 132
... SIO1CR2<SIORXD> have been read.) 0: Transmit operation was normal. 1: Error occurred during transmission. 0: Receive operation was normal. 1: Error occurred during reception (Initial value: **** ****) Transmit data are set, or received data are stored. 86FP24-130 TMP86FP24 R/W “0”). Read only R/W 2007-08-24 ...
Page 133
... SCK1 4 MHz) Clock Baud Rate 13 fc/2 0.47 Kbps 8 fc/2 15.25 Kbps 6 fc/2 61.04 Kbps 5 fc/2 122.07 Kbps 4 fc/2 244.14 Kbps 3 fc/2 488.28 Kbps 2 fc/2 976.56 Kbps External External (1 Kbit 1,024 bits) pin is used as the serial clock SCKL SCKH 4/fc SCKL SCKH 86FP24-131 TMP86FP24 2007-08-24 ...
Page 134
... SCK1 SI1 pin Bit7 Bit6 Shift register *******7 Bit5 Bit4 Bit3 Bit2 (a) Leading-edge shift Bit5 Bit4 Bit3 Bit2 ******76 *****765 ****7654 ***76543 **765432 *7654321 (b) Trailing-edge shift Figure 2.14.5 Shift Edges 86FP24-132 TMP86FP24 Bit1 Bit0 76543210 Bit1 Bit0 76543210 2007-08-24 ...
Page 135
... SCK1 SI1 pin Received-data store pin SCK1 SI1 pin Received-data store “1”) 86FP24-133 TMP86FP24 “0” 2007-08-24 ...
Page 136
... SIO1CR1<SIOS> to “0”, make sure SIO1SR<SIOF> “0” and SIO1SR<TXERR> transfer error), write the data to be transferred, and then set SIO1CR1<SIOS> “1”. 86FP24-134 sequentially in the direction “1”. Before starting to “0” in the external clock mode (No TMP86FP24 selected using 2007-08-24 ...
Page 137
... SIO stops transferring (SIO1SR<SIOF> “0”) after the last data byte is transmitted (the signal at the pin rises). SCK1 Last byte SIO1CR1<SIOS> “0” causes the SIO to stop transferring. INTSIO1 is accepted. 6 SCK SODH “0” within the INTSIO1 interrupt service routine, 86FP24-135 TMP86FP24 B0 T (16.5/fc to 32.5/fc) SODH “0”) “0”) 2007-08-24 ...
Page 138
... SO1 pin SIO1SR<TXF> INTSIO1 Clearing SIO1CR1<SIOS> within the interrupt service routine Figure 2.14.9 SIO1CR1<SIOS> Clear Timing 86FP24-136 T SODH SIO1CR1<SIOS> “0” causes the SIO to stop transferring TMP86FP24 2007-08-24 ...
Page 139
... LD (SIO1CR1), 10000111B INTSIO1 (INTSIO1 service routine): LD (SIO1CR1), 00000111B TEST (SIO1SR). 3 JRS T, NOERR LD (SIO1CR1), 01000111B Error handling NOERR: END: 86FP24-137 TMP86FP24 “1”) but “1”). ; PORT setting. P07 ( ) input and P06 (SO1) output. SCK1 ; Sets and SO1. SCK1 ; IMF Enables INTSIO1 (EF10). ...
Page 140
... B1 INTSIO1 is accepted. “0” is written), the transfer of the last byte is completed and more “1”), do not supply more transfer clock pulses than the pin. SCK1 86FP24-138 TMP86FP24 External SCK input SIO1CR1<SIOS> “1” causes the SIO to start transferring. Transmit data are written ...
Page 141
... Note attempt is made to start transferring after a receive error has been detected, the SIO fails to work normally. Before starting transferring, set SIO1CR1<SIOINH> “1” to force the SIO to halt. 86FP24-139 TMP86FP24 in the direction selected “1”. ...
Page 142
... SIO1SR<RXERR> flag, the INTSIO1 isn’t generated SCK1 86FP24-140 TMP86FP24 SIO1CR1<SIOS> “0” causes the SIO to stop transferring. All data bytes have been read from SIO1BUF. pin.) 2007-08-24 ...
Page 143
... LD (SIO1CR1), 10010111B INTSIO1 (INTSIO1 service routine): LD (SIO1CR1), 00010111B LD (SIO1CR1), 01010111B Receive data reading Checks a checksum or the like to see if the received data are normal. END: 86FP24-141 TMP86FP24 ; PORT setting P07 ( ) input and P05 (SI1) input. SCK1 Sets and SI1. ; SCK1 ; IMF m 0 ...
Page 144
... SIO to stop transferring. “1” causes INTSIO1 is accepted. (In the interrupt service routine, clear SIO1CR1<SIOS> to “0” and confirm SIO1SR<SIOF> “0”, SIO1SR<RXERR> “0”, and then, read data from SIO1BUF. ) 86FP24-142 TMP86FP24 External SCK input ...
Page 145
... SIO1SR<SIOF> “0”, SIO1SR<RXERR> “0”, and then, read data from SIO1BUF.) “1”), do not supply more transfer clock pulses than the pin. SCK1 86FP24-143 TMP86FP24 SIO1CR1<SIOS> “0” causes the SIO to stop transferring. SIO1CR1<SIOINH> “1” ...
Page 146
... Clearing of SIO1CR1<SIOS> should be executed within the INTSIO1 service routine or should be executed after confirmation of SIO1SR<RXF> Setting SIO1CR1<SIOINH> to “1” causes the SIO to immediately stop the x transmission/reception sequence even if any byte is being transmitted or received. 86FP24-144 TMP86FP24 transmit data bytes as specified SIO1CR2<SIORXD> have been “ ...
Page 147
... 86FP24-145 TMP86FP24 “0” in the “1” to start transferring. SIO1CR1<SIOS> “0” causes the SIO to stop transferring All data bytes are read from SIO1BUF. 2007-08-24 ...
Page 148
... SIO1CR2<SIORXD> have been received continuously again without clearing the SIO1SR<RXERR> flag, the INTSIO1 isn’t generated. 86FP24-146 an error flag (SIO1SR<TXERR> “1”). “1”) (if eight clock pin) (SIO1SR<RXERR>) TMP86FP24 or “1”) but 2007-08-24 ...
Page 149
... JRS T, TXNOER LD (SIO1CR1), 01100111B Error handling JP END TXNOER: Receive-data reading Checks a checksum or the like to see if the received data are correct. END: 86FP24-147 TMP86FP24 ; PORT setting. P07 ( ) input, P06 (SO1) output, and SCK1 P05 (SI1) input. ; Sets , SO1, and SI1. SCK1 ; IMF m 0 ...
Page 150
... SIO1CR1<SIOS> “1” causes causes the SIO to stop transferring. “0”, SIO1SR<TXERR> “0” and 86FP24-148 TMP86FP24 SIO1CR1<SIOS> “1” causes the SIO to start transferring. ...
Page 151
... SIO1SR<TXERR>. Since SIO1SR<TXERR> has occurred, the SIO is forced to halt (SIO1CR1<SIOINH> “1”), do not supply more transfer clock pulses than the SCK1 86FP24-149 TMP86FP24 Eighth clock pulse after a specified number of bytes are exceeded. SIO1CR1<SIOS> “0” causes the SIO to stop transferring ...
Page 152
... Address bus ROMCCR Mode selection Enable control Read signal Compa- rator RCAD0H RCAD0L Figure 2.15.1 Program Patch Logic 8 ROM ROM chip select signal Read signal Data selection 8 8 circuit FEH RCDT0H RCDT0L Address 1 Address 2 BANK0 BANK1 BANK2 BANK3 86FP24-150 TMP86FP24 Data bus 8 2007-08-24 ...
Page 153
... Disable 01: Address jump mode 10: 1-byte data replacement mode 11: 2-byte data replacement mode 00: Disable 01: Address jump mode 10: 1-byte data replacement mode 11: 2-byte data replacement mode 00: Disable 01: Address jump mode 10: 1-byte data replacement mode 11: 2-byte data replacement mode 86FP24-151 TMP86FP24 R/W 2007-08-24 ...
Page 154
... Areas which should not be specified in 1FH ROMCCR the program correction address 4108H 78H registers (RCADx) 4109H xxH 2 bytes 410AH xxH 410BH xxH 86FP24-152 TMP86FP24 (Initial value: 0000 0000 RCAD0L (1FC1H) (Initial value: 0000 0000 RCDT0L (1FC3H) (Initial value: 0000 0000) ...
Page 155
... Note 3: To set the jump target in the RAM for the address jump mode, an address trap of the RAM address must be disabled through the WDTCR1 and WDTCR2 before setting the ROMCCR. Note 4: In the address jump mode, when a read instruction is executed for the address specified in the RCADx, FEH is read from the address. 86FP24-153 TMP86FP24 2007-08-24 ...
Page 156
... Program correction address registers Memory (RCAD0H) (RCAD0L) D2H 54H D253H 55H 0Ah D254H 50h JP 0300H D255H 12h D256H D257H 4BH D258H 40H After the address jump mode is set. 86FP24-154 TMP86FP24 Replacement FEH (RCDT0L) Program 00H correction 03H (RCDT0H) data registers 2007-08-24 ...
Page 157
... Sets the ATRAP control code to WDTCR2. HL, RCAD0L (HL), 0C020H ; Sets the program correction address registers. HL, RCDT0L (HL), 0200H ; Sets the program correction data registers. (ROMCCR), 00000001B ; Sets the program correction control register. 0200H Patch program 022DH JP C086H 022FH Jump Jump 86FP24-155 TMP86FP24 2007-08-24 ...
Page 158
... Program correction address registers Memory (RCAD0H) (RCAD0L) D2H 56H D253H 55H D254H 0AH D255H 50H LD (50H), 34H 34H D256H 12h D257H 4BH D258H 40H After the 1-byte data replacement mode is set. 86FP24-156 TMP86FP24 Replacement Program correction (RCDT0L) data registers 2007-08-24 ...
Page 159
... Set the corrective data in the program correction data registers (RCDTxL, RCDTxH). The program patch logic enables the 2-byte data replacement mode when the BANKxCNT in the ROMCCR is set to “11B” after all these registers are set. 86FP24-157 TMP86FP24 2007-08-24 ...
Page 160
... Memory (RCAD0H) (RCAD0L) D2H 54H D253H 55H 0Ah FCH D254H 50h 01H JR 0D257H D255H D256H 12H D257H 4BH Jump D258H 40H After the 2-byte data replacement mode is set. 86FP24-158 TMP86FP24 Replacement (RCDT0L) Program correction (RCDT0H) data registers First operation code 2007-08-24 ...
Page 161
... FFFFH Figure 2.15.8 Example of Replacing the Data (2-byte data replacement mode) HL, RCAD0L ; Sets the program correction address registers. (HL), 0C020H HL, RCDT0L (HL), 0CC33H ; Sets the program correction data registers. (ROMCCR), 00000011B ; Sets the program correction control register. 33H Corrective data CCH 86FP24-159 TMP86FP24 2007-08-24 ...
Page 162
... The FLASH memory is constructed of 384 pages FLASH and one page size is 128 bytes x (384 pages u 128 bytes The TMP86FP24 incorporates a 128-byte temporary data buffer. The data written to x FLASH is temporarily stored in this data buffer. After 128 bytes data have been written to the temporary data buffer, the writing to FLASH automatically starts by page writing (the 128 bytes data are written to specified page of FLASH simultaneously) ...
Page 163
... Differences among Product Series The specifications of the FLASH product (TMP86FP24) are different from those of the emulation chip (TMP86C948) and masked ROM product (TMP86CP24) as listed below. See 2.17.2 “Control ” for explanations about the control registers. Rewriting the EEPCR register <EEPMD, EEPRS, MNPWDW> ...
Page 164
... FLASH Memory Configuration 128 consecutive bytes in the FLASH area are treated as one group, which is defined as a page. The TMP86FP24 incorporates a one-page temporary data buffer. Writing data to FLASH is temporarily stored in this 128-byte data buffer. After 128 bytes data have been written to the temporary data buffer, these data are written to specified page of FLASH at a time ...
Page 165
... Overflow EN with write data counter Clear Request to CP generate an interrupt vector EEPSR RD signal EEPCR EEPSR 86FP24-163 TMP86FP24 Address input Data input FLASH Memory End of write VIN Regulator CPU WAIT signal FLASH warm-up CP counter R Overflow Q R 2007-08-24 ...
Page 166
... When write to or read from the flash memory, make sure that the EEPSR<EWUPEN> is “1” by software. Once the MNPWDW is rewritten from “0” to “1” by software, keep performing software based polling until the EEPSR<EWUPEN> becomes “1”. 86FP24-164 TMP86FP24 0 (Initial value: 1100 *011) Program Execution Area RAM/ ...
Page 167
... EEPSR. Operating (Power on) status Temporary data Writing buffer empty “1” is detected in the non-maskable interrupt service routine, a write is not 86FP24-165 TMP86FP24 0 (Initial value: **** *010) Read Halt (Power off) or warm-up only Disable /fc [s] (if SYSCK “0” ...
Page 168
... Reserved Reserved 111 Reserved Reserved NORMAL1/2 Mode fc 8 MHz fc 4 MHz fc 2 MHz 8.19 16.38 32.77 4.10 8.19 16.38 2.05 4.10 8.19 1.02 2.05 4.10 0.51 1.02 2.05 86FP24-166 TMP86FP24 0 (Initial value: **** *000) FLASH Product (TMP86FP24) All operation Modes R/W Typ (Regardless of register settings and the system clock.) SLOW1/2 Mode fc 1 MHz fs 32.768 kHz 65.54 3.91 32.77 1.95 16.38 0.98 8.19 0.49 4.10 0.24 2007-08-24 ...
Page 169
... RAM area. Executing a write instruction to the EEPCR<EEPMD> in the FLASH area does not change its setting. Note 3: In the masked ROM product, executing a write instruction to the EEPCR<EEPMD> changes its setting; however, the new setting does not take effect. 86FP24-167 TMP86FP24 2007-08-24 ...
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... After this, if writing to FLASH starts again, HL, 8000H (EEPCR), 3FH çSet EEPCR<EEPRS> to “1”. çNOP (Do not execute write or read instruction immediately after setting EEPCR<EEPRS>.) A,(HL) çReads the data of address 8000H (Write or read instruction to the flash memory). 86FP24-168 TMP86FP24 “1”, the 2007-08-24 ...
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... FLASH control circuit Normal operation status Figure 2.17.5 Write Data Counter Initialization and Write Forcible Stop Data 0’ Data 1’ “1” / /fs [s] Overflow 0 Normal operation Warm up in progress (CPU WAIT) 86FP24-169 TMP86FP24 Data 2’ 2007-08-24 ...
Page 172
... STOP Mode (when EEPCR<MNPWDW> To Return to a NORMAL Mode 10 STOP warm-up time 2 /fc [s] STOP warm-up time 2 “1”). Usually software-based polling should be “0” /fs (SYSCK “1”) until EWUPEN becomes 3 86FP24-170 TMP86FP24 “1”) To Return to a SLOW Mode 3 /fs [s] 10 /fc [s] 2007-08-24 ...
Page 173
... FLASH control circuit status Figure 2.17.6 Software-based Power Control for the FLASH Control Circuit (EEPCR<MNPWDW>) “0”. 0 Specify MNPWDW / /fs [s] RAM area Overflow 0 Warm up in progress Power-off state (CPU is operating) 86FP24-171 TMP86FP24 1 Software polling FLASH area 0 Normal operation 2007-08-24 ...
Page 174
... SET (EEPCR). 0 sLOOP1: TEST (EEPSR). 1 JRS T, sLOOP1 JP MAIN 86FP24-172 TMP86FP24 ; Disable an interrupt (IMF m “0”). ; Clear the binary counter if the watchdog timer is in use. ; Clear the EEPCR<MNPWDW> to “0”. ; Set the EEPCR<MNPWDW> to “1”. ; Monitor the EEPSR<EWUPEN> register. ...
Page 175
... STOP mode forcibly turns off the power Specify ATPWDW / /fs [s] Overflow 0 Power-off state Warm up in progress CPU WAIT IDLE or SLEEP mode FLASH area or RAM area 86FP24-173 TMP86FP24 “1”). If the 0 Normal operation NORMAL or SLOW mode 2007-08-24 ...
Page 176
... Note 4: When write the data to Flash memory from RAM area, disable all the non-maskable interrupt by clearing interrupt master enable flag (IMF) to “0” beforehand. “1”). After 1 to 127 bytes are saved to the temporary 86FP24-174 TMP86FP24 2007-08-24 ...
Page 177
... For the emulation chip the value specified in the EEPEVA register.) 7. Set the EEPCR with “CBH” (to disable a write to the FLASH). Note: See (2), “Method of specifying an address for a write to the FLASH”, for a description about the FLASH address to be specified at step 5 above. 86FP24-175 TMP86FP24 2007-08-24 ...
Page 178
... LD (HL), 0CBH Note: If the BFBUSY is “1”, executing a read instruction or fetch to the FLASH area causes “FFH” read. Fetching “FFH” results in a software interrupt occurring. 86FP24-176 TMP86FP24 ; Disable an interrupt (IMF m “0”) ; Specify the EEPCR register address. ; Specify a write address. ...
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... TMP86FP24 0CH 0DH 0EH 0FH 1CH 1DH 1EH 1FH 2CH 2DH 2EH 2FH 3CH 3DH 3EH 3FH 4CH ...
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... Erasing Writing Overflow 3 0 127 Write time (Typically 4 ms) 128 bytes are written at a time. Data 2 Data 127 Data before writing Overflow 3 127 0 Write time (Set by EEPEVA register) 86FP24-178 TMP86FP24 Data after writing Write completed Data after writing Write completed 2007-08-24 ...
Page 181
... Serial PROM Mode 2.18.1 Outline The TMP86FP24 has a 2 Kbytes BOOT ROM for programming to FLASH memory. This BOOT ROM is a mask ROM that contains a program to write the FLASH memory on board. The BOOT ROM is available in a serial PROM mode and it is controlled by P11 pin, BOOT pin (P23), TEST pin and pins ...
Page 182
... Serial PROM Mode Setting 2.18.3.1 Serial PROM Mode Control Pins To execute on-board programming, start the TMP86FP24 in serial PROM mode. Setting of a serial PROM mode is shown in Table 2.1.2. Table 2.18.2 Serial PROM Mode Setting RESET 2.18.3.2 Pin Function In the serial PROM mode, TXD (P06) and RXD (P05) pins are used as a serial interface pin ...
Page 183
... To set a serial PROM mode, connect device pins as shown in Figure 2.18.2. TMP86FP24 XIN XOUT GND GND Figure 2.18.2 Serial PROM Mode Port Setting VDD (2.7 V~3.6 V) VDD AVDD VAREF (BOOT) P23 P11 GND TXD(P06) RXD(P05) RESET Serial PROM mode TEST MCU mode 86FP24-181 TMP86FP24 External control 2007-08-24 ...
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... Symbol Clock (fc) Tssup - - Tsint - RXsup 110000 RESET pin.) However, drive the pins carefully not 86FP24-182 TMP86FP24 Tssup Rstf Warm-up Serial PROM mode Setup time for Serial PROM mode (Rxsup) Matching data (5Ah) input Required Minimum Time MHz MHz 1 ms ...
Page 185
... VDD by setting a jumper on the application board. VDD (2.7 V~3.6 V) VDD VDD (Note6) GND Reset (Note2) control (Note1) (Note5) Logic IC (Note4) MCU mode GND RESET 86FP24-183 TMP86FP24 Level To PC Converter VDD (Note3) RC power on reset circuit External control board pin to logic ICs (Schmitt input 2007-08-24 ...
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... Baud rate (Default): 9600 bps Data length: 8 bits Parity addition: None Stop bit length: 1 bit Table 2.18.5 Baud Rate Modification Data Baud Rate Modification Data Baud rate (bps) 76800 04H 05H 06H 07H 0AH 62500 57600 38400 31250 86FP24-184 TMP86FP24 18H 28H 19200 9600 2007-08-24 ...
Page 187
... Note 3: An external controller should transmit a matching data repeatedly till the TMP86FP24 transmit an echo back data. Above number indicates a transmission number of times of matching data till transmission of echo back data. 2.18.5 Command There are five commands in serial PROM mode. After reset release, the TMP86FP24 waits a matching data (5AH). S Table 2.18.7 Command in Serial PROM Mode ...
Page 188
... Product discrimination code output mode The product discrimination code is output as a 13-byte data, that includes the start address and the end address of ROM (In case of TMP86FP24, the start address is 4000H and the end address is FFFFH). Therefore, the controller can recognize the device information by using this function. ...
Page 189
... If a password error occurs, the UART function of TMP86FP24 stops without returning error code to the controller. Therefore, when a password error occurs, the TMP86FP24 should be ...
Page 190
... The receive data in the 1st byte is the matching data. When the boot program starts in serial PROM mode, TMP86FP24 (Mentioned as “device” hereafter) waits for the matching data (5AH) to receive. Upon receiving the matching data, it automatically adjusts the UART’s initial baud rate to 9.600 bps. ...
Page 191
... After the SUM calculation, the device sends the SUM data to the controller. After sending the end record, the controller can judge that the transmission has been terminated correctly by receiving the checksum. 14. After sending the SUM, the device waits for the next operation command data. 86FP24-189 TMP86FP24 16 MHz. 2007-08-24 ...
Page 192
... However necessary to specify the password count storage addresses and the password comparison start address even though blank product password error occurs, the UART function of TMP86FP24 stops without returning error code to the controller. Therefore, when a password error occurs, the ...
Page 193
... Note 6: Do not send only end record after transferring of password string. If the TMP86FP24 receives the end record only after reception of password string, it does not operate correctly. Note 7: When the FLASH power supply is turned off in user’s program by setting EEPCR<MNPWDW>, be sure to disable the watchdog timer (WDT clear the binary counter of WDT immediately before ...
Page 194
... The data of data record is written to specified RAM by the receiving data. Since after receiving an end record, the device starts to calculate the SUM, the controller should wait the SUM after sending the end record. If receive error or Intel Hex format error occurs, the UART function of TMP86FP24 stops without returning error code to the controller. 6. ...
Page 195
... For details on how to calculate the SUM, refer to 2.18.9 “Checksum (SUM)”. 5. After sending the SUM, the device waits for the next operation command data. Transfer Data from TMP86FP24 to Baud Rate 9600 bps (Baud rate auto set) ...
Page 196
... The 7th and the 19th bytes are the product discrimination code. For details, refer to 2.18.12 “Product Discrimination Code”. 5. After sending the SUM, the device waits for the next operation command data. Transfer Data from TMP86FP24 to Baud Rate 9600 bps (Baud rate auto set) ...
Page 197
... FLASH Memory Writing Data Format FLASH area of TMP86FP24 consists of 384 pages and one page size is 128 bytes. Writing to FLASH is executed by page writing. Therefore necessary to send 128 bytes data (for one page) even though only a few bytes data are written. Figure 2.18.5 shows an organization of FLASH area ...
Page 198
... FFC0H FFD0H FFE0H FFF0H Note: “F” shows the 1st address of each page and “E” shows the last address of each page. Figure 2.18.5 Organization of FLASH Area Page 0 Page 1 Page 382 Page 383 86FP24-196 TMP86FP24 2007-08-24 ...
Page 199
... Transmit Data 62H, 62H, 62H 63H, 63H, 63H A1H, A1H, A1H A3H, A3H, A3H Note: If password error occurs, the TMP86FP24 doesn’t send error codes. 2.18.9 Checksum (SUM) (1) Calculation method SUM consists of byte byte... byte, the checksum of which is returned in word as the result. ...
Page 200
... If a receive error or Intel Hex format error occurs, the UART function of TMP86FP24 stops without returning error code to the controller. In the following cases, an Intel Hex format error occurs: ...