tmp86fp24 TOSHIBA Semiconductor CORPORATION, tmp86fp24 Datasheet - Page 147

• Manufacturer Part Number: tmp86fp24
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SIO1CR1<SIOS>
SIO1SR<SIOF>
SIO1SR<SEF>
SO1 pin
SIO1SR<TXF>
SI1 pin
SIO1SR<RXF>
INTSIO1
SCK1
pin






Figure 2.14.15 SIO1CR1<SIOS> Clear Timing (Transmit/receive mode)
Received-data read and transmit-data set timing
received, reading the received data and writing the next transmit data should be
executed after confirmation of SIO1SR<RXF>
SIO1CR1<SIOS> is cleared to “0” in the INTSIO1 interrupt service routine. Before
transferring the next data after clearing SIO1CR1<SIOS> to “0”, make sure
SIO1SR<SIOF>
external clock mode (No transfer error and no receive error), read the received data,
and then write the transmit data and set SIO1CR1<SIOS>
Note 1: An INTSIO1 interrupt occurs when the last bit of the last data byte is received.
Note 2: When writing to and reading from SIO1BUF, make sure that the number of data
Note 3: When as many data bytes as specified in SIO1CR2<SIORXD> are read,
Note 4: In the transmit/receive mode, setting SIO1CR1<SIOINH> to “1” to force the SIO to
Note 5: If a transfer sequence is started after a transmit or receive error has been detected,
After as many bytes as specified in SIO1CR2<SIORXD> have been transmitted and
bytes to transfer is as specified in SIO1CR2<SIORXD>. If the number is not equal
to the value specified in SIO1CR2<SIORXD>, the SIO does not run normally.
SIO1SR<RXF> is cleared to “0”.
halt will cause received data to be discarded.
the SIO does not run normally. Before starting transferring, set SIO1CR1<SIOINH>
Z
A
“1” to force the SIO to halt.
7
7
C
X
6
6
C
X
5
5
“0”, SIO1SR<TXERR>
C
X
4
4
C
X
3
3
C
X
2
2
86FP24-145
C
X
1
1
C
X
0
0
W
D
7
7
W
D
6
6
W
D
5
5
W
D
4
4
W
D
3
3
“0” and SIO1SR<RXERR>
W
D
2
2
W
D
1
1
W
“1” or should be executed after
0
D
0
All data bytes are
read from SIO1BUF.
SIO1CR1<SIOS>
the SIO to stop transferring.
“1” to start transferring.
TMP86FP24

2007-08-24
“0” causes
“0” in the