tmp86fp24 TOSHIBA Semiconductor CORPORATION, tmp86fp24 Datasheet - Page 47

• Manufacturer Part Number: tmp86fp24
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Internal reset
1.6.2
1.6.3
1.6.4
Instruction
execution
Note 1: Address “a” is in the SFR or on-chip RAM (WDTCR1<ATAS>
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Address-trap-reset
fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”) or the SFR
area, address-trap-reset and the flash reset will be generated. The reset time is maximum
24/fc [s]  2
Note: The operating mode under address trapped is alternative of reset or interrupt. Address
Watchdog Timer Reset
System-clock-reset
prevent dead lock of the CPU (The oscillation is continued without stopping).
the maximum reset period is 24/fc [s]  2
If the CPU should start looping for some cause such as noise and an attempt be made to
Refer to Section 2.4 “Watchdog Timer”.
If the condition as follows is detected, the system clock reset occurs automatically to
When the system clock reset is generated, the flash reset is also generated. Therefore,
x
x
x
trap or no address trap can be selected by WDTCR1<ATAS> for the internal RAM.
In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
JP a
10
/fc [s] (65.5 Ps at 16.0 MHz).
max 24/fc [s]
Address trap is occurred
Figure 1.6.2 Address-trap-reset
for Flash reset
2
10
/fc [s]
86FP24-45
10
/fc [s] (65.5 Ps at 16.0 MHz).
4/fc to 12/fc [s]
“1”) space.
Reset release
16/fc [s]
Instruction at address r
TMP86FP24
2007-08-24