tmp86fp24 TOSHIBA Semiconductor CORPORATION, tmp86fp24 Datasheet - Page 93
tmp86fp24
Manufacturer Part Number
tmp86fp24
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86FP24.pdf
(217 pages)
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(2) Event counter mode
“H” Width
“L” Width
the TC3 pin can have its polarity inverted using the TC3SEL register TC3INV bit.
When TC3SEL<TC3INV> “0”, the counter counts up on the rising edge of the TC3 pin
input and when its value matches the TC3DRA set value, it is cleared while at the
same time generating an INTTC3 interrupt. When TC3SEL<TC3INV>
counter counts up on the falling edge of the TC3 pin input and when its value matches
the TC3DRA set value, it is cleared while at the same time generating an INTTC3
interrupt.
of the TC3 pin. Therefore, if the TC3 pin keeps high level after the rising, the detection
of match is not executed and INTTC3 is not generated until the level of TC3 pin
becomes low. When TC3SEL<TC3INV>
rising edge of the TC3 pin. Therefore, if the TC3 pin keeps low level after the falling,
the detection of match is not executed and INTTC3 is not generated until the level of
TC3 pin becomes high.
machine cycles are required for both the “H” and “L” levels of the pulse width.
TC3CR<ACAP> to “1” (Auto-capture function).
(RD instruction) of TC3DRB. Loading the contents of up counter is not synchronized
with counting up. The contents of over flow (FFH) and 00H can not be loaded correctly.
It is necessary to consider the count cycle.
In this mode, events are counted on the edge of the TC3 pin input. The input pulse at
When TC3SEL<TC3INV> “0”, the detection of match is executed at the falling edge
The minimum input pulse width of the TC3 pin is shown in Table 2.8.2. One or more
The current contents of up counter are loaded into TC3DRB by setting
The contents of up counter can be easily confirmed by executing the read instruction
Table 2.8.2 Source Clock (External clock) for Timer/Counter
NORMAL1/2, IDLE1/2 Modes
2
2
2
2
/fc
/fc
Minimum Input Pulse Width [s]
86FP24-91
SLOW1/2, SLEEP1/2 Modes
“1”, the detection of match is executed at the
2
2
2
2
/fs
/fs
TMP86FP24
2007-08-24
“1”, the
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