tmp86fp24 TOSHIBA Semiconductor CORPORATION, tmp86fp24 Datasheet - Page 105
tmp86fp24
Manufacturer Part Number
tmp86fp24
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86FP24.pdf
(217 pages)
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RT clock
RT clock
RXD pin
Internal receive data
RXD pin
Internal receive data
2.10.4 Transfer Rate
2.10.5 Data Sampling
as follows.
transfer clock and transfer rate are determined as follows:
until a start bit is detected in RXD pin input. RT clock starts detecting “L” level of the RXD
pin. Once a start bit is detected, the start bit, data bits, stop bit (s), and parity bit are
sampled at three times of RT7, RT8, and RT9 during one receiver clock interval (RT clock).
(RT0 is the position where the bit supposedly starts). Bit is determined according to
majority rule (the data are the same twice or more out of three samplings).
The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate shown
When TC5 is used as the UART transfer rate (when UARTCR1<BRG> “110”), the
The UART receiver keeps sampling input using the clock selected by UARTCR1<BRG>
BRG
000
001
010
011
100
101
Transfer clock
Transfer rate
RT0
RT0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
76800 [baud]
38400
19200
9600
4800
2400
16 MHz
Start bit
Start bit
Start bit
Start bit
Figure 2.10.4 Data Sampling
Transfer clock
Table 2.10.2 Transfer Rate
TTREG5 set value
TC5 source clock
16
86FP24-103
a) Without noise rejection circuit
Source Clock
38400 [baud]
19200
b) With noise rejection circuit
9600
4800
2400
1200
8 MHz
Bit0
Bit0
Bit0
Bit0
19200 [baud]
9600
4800
2400
1200
600
4 MHz
TMP86FP24
2007-08-24
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