tmp86fp24 TOSHIBA Semiconductor CORPORATION, tmp86fp24 Datasheet - Page 88
tmp86fp24
Manufacturer Part Number
tmp86fp24
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86FP24.pdf
(217 pages)
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(2) Event counter mode
“H” Width
“L” Width
contents of TC2DR are compared with the contents of the up counter. If a match is
found, an INTTC2 interrupt is generated, and the counter is cleared. The minimum
input pulse width of the TC2 pin is shown in Table 2.7.2. Two or more machine cycles
are required for both the “H” and “L” levels of the pulse width. Match detect is executed
on the falling edge of the TC2 pin. A match can not be detected and INTTC2 is not
generated when the pulse is still in a falling state.
In this mode, events are counted on the rising edge of the TC2 pin input. The
Example: Sets the event counter mode and generates an INTTC2 interrupt 640 counts later.
Table 2.7.2 Timer/Counter 2 External Clock Source
NORMAL1/2, IDLE1/2 Modes
LDW
DI
SET
EI
LD
LD
2
2
3
3
/fc
/fc
Minimum Input Pulse Width [s]
(TC2DR), 640
(EIRE). 4
(TC2CR), 00011100B
(TC2CR), 00111100B
86FP24-86
SLOW1/2, SLEEP1/2 Modes
;
;
;
;
;
;
Sets TC2DR.
IMF
Enables INTTC2 interrupt.
IMF
TC2CK m “111”, TC2M m “0”
Starts TC2.
2
2
3
3
/fs
/fs
“0”
“1”
TMP86FP24
2007-08-24
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