tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 182

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tmp89fm42

Manufacturer Part Number
tmp89fm42
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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14. 8-bit Timer Counter (TC0)
RA002
Timer counter 00 mode register
T00MOD
(0x002A)
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Set T00MOD while the timer is stopped. Writing data into T00MOD is invalid during the timer operation.
Note 3: In the 8-bit timer/event modes, the TFF0 setting is invalid. In this mode, when the
Note 4: When EIN0 is set to "1" and the external clock input is selected as the source clock, the TCK0 setting is ignored.
Note 5: When the T001CR<TCAS> bit is "1", timer 00 operates in the 16-bit mode. The T00MOD setting is invalid and timer 00
Note 6: When the 16-bit mode is selected at T001CR<TCAS>, the timer start is controlled at T001CR<T01RUN>. Timer 00 is not
function output pins in the port setting, the pins always output the "H" level.
cannot be used independently in this mode. When the
setting, the pins always output the "H" level.
started by writing data into T001CR<T00RUN>.
Read/Write
Bit Symbol
After reset
TCM0
DBE0
TCK0
TFF0
EIN0
Timer F/F0 control
Double buffer control
Operation clock selection
Selection for using external source
clock
Operation mode selection
TFF0
R/W
7
1
DBE0
R/W
6
1
5
0
Page 168
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Clear
Set
Disable the double buffer
Enable the double buffer
Select the internal clock as the source clock.
Select an external clock as the source clock. (the falling edge of the
TC00 pin)
8-bit timer/event counter modes
8-bit timer/event counter modes
8-bit pulse width modulation output (PWM) mode
8-bit programmable pulse generate (PPG) mode
PWM0
SYSCR1<DV9CK>
TCK0
R/W
4
0
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
NORMAL1/2 or IDLE1/2 mode
fcgck
= "0"
and
10
PPG0
11
8
6
4
2
pins are set to the function output pins in the port
3
0
SYSCR1<DV9CK>
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
PWM0
fcgck
EIN0
= "1"
fs/2
fs/2
R/W
2
0
4
3
8
6
4
2
and
PPG0
SLOW1/2 or SLEEP1
1
0
pins are set as the
TCM0
R/W
TMP89FM42
mode
fs/2
fs/2
fs/2
-
-
-
-
-
4
3
2
0
0

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