tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 212

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14. 8-bit Timer Counter (TC0)
RA002
T001CR<T00RUN>
T00MOD<TFF0>
Source clock
Counter
Write to T00PWM
Write to T01PWM
Double buffer
PWMAD3 ~ 0
PWMDUTY
PWM0 pin output
INTT00 interrupt request
INTT00 interrupt request
(Example)
Write m (0001)
Becomes the level selected at
TFF0 while the timer is stopped
Write k
km
km (0001)
0001
Operate TC00 and TC01 in the 12-bit PWM mode with the operation clock of fcgck/2 and output a duty pulse nearly equiva-
lent to 14.0625 Ps in 51.2Ps cycles (fcgck = 10 MHz)
(Actually, output a duty pulse of 225 Ps in total in 16 cycles (819.2 Ps))
SET
SET
LD
DI
SET
EI
LD
LD
LD
LD
timer is stopped, the set value is immediately stored in T01+00PWM.
When write instructions are executed on T00PWM and T01PWM in this order while the
Figure 14-15 12-bit PWM Mode Timing Chart
Timer start
(Duty pulse)
0
km
1
256 counts
(Cycle 1)
(P7FC).1
(P7CR).1
(POFFCR0),0x10
(EIRH).4
(T01MOD),0xF2
(T00PWM),0x65
(T00PWM),0x04
(T001CR),0x06
When the double buffer is enabled (T01MOD<DBE1>=”1”)
Match detection
km
km
+1
(Duty pulse)
256
Overflow
Counter
clear
Interrupt request
0
km
256 counts
1
(Cycle 2)
Page 198
Match detection
km
; Sets P7FC1 to "1"
; Sets P7CR1 to "1"
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects the 16-bit PWM mode and fcgck/2
; Sets the timer register (duty pulse)
; (14.0625Ps u 16) / (2/fcgck) = 0x465
; Sets the timer register (duty pulse)
; Starts TC00 and TC01
km
+1
256
Overflow
(Duty pulse)
Counter
clear
Interrupt request
0
km+1
1
256 counts
Additional pulse
(Cycle 9)
Match detection
km
km
+1
(Duty pulse)
256
Overflow
Interrupt request
Counter
clear
0
km
256 counts
(Cycle 16)
1
Write s (0011)
Write r
rs (0011)
Match detection
km
km
+1
TMP89FM42
(Duty pulse)
256
rs
Counter
clear
0011
Interrupt reques
0
(Cycle 17)
rs
1
rs