tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 91

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
5.3.4 Setting an overflow detection signal of the 8-bit up counter
5.3.5 Writing the watchdog timer control codes
Note: When a watchdog timer interrupt is generated while another interrupt, including a watchdog timer interrupt, is already
source clock.
operation.
flow time of the 8-bit up counter and within the clear time.
detected through interrupts generated by watchdog timer interrupt request signals.
restored from malfunctions and deadlock.
Clear the 8-bit up counter at a point after
half of its overflow time and within a peri-
od of the overflow time minus 1 source
clock cycle.
Clear the 8-bit up counter at a point after
half of its overflow time and within a peri-
od of the overflow time minus 1 source
clock cycle.
Note:The 8-bit up counter source clock operates out of synchronization with WDCTR<WDTEN>. Therefore, the first
WDCTR<WDTOUT> selects a signal to be generated when the overflow of the 8-bit up counter is detected.
accepted, the new watchdog timer interrupt is processed immediately and the preceding interrupt is put on hold. Therefore,
if watchdog timer interrupts are generated continuously without execution of the RETN instruction, too many levels of nest-
ing may cause a malfunction of the microcontroller.
The watchdog timer control codes are written into WDCDR.
By writing 0x4E (clear code) into WDCDR, the 8-bit up counter is cleared to "0" and continues counting the
When WDCTR<WDTEN> is "0", writing 0xB1 (disable code) into WDCDR disables the watchdog timer
To prevent the 8-bit up counter from overflowing, clear the 8-bit up counter in a period shorter than the over-
By designing the program so that no overflow will occur, the program malfunctions and deadlock can be
By applying a reset to the microcomputer using watchdog timer reset request signals, the CPU can be
Note:If the overflow of the 8-bit up counter and writing of 0x4E (clear code) into WDCDR occur simultaneously, the
Example: When WDCTR<WDTEN> is "0", set the watchdog timer detection time to 2
1. When the watchdog timer interrupt request signal is selected (when WDCTR<WDTOUT> is "0")
2. When the watchdog timer reset request signal is selected (when WDCTR<WDTOUT> is "1")
overflow time of the 8-bit up counter after WDCTR<WDTEN> is set to "1" may get shorter by a maximum of 1
source clock. The 8-bit up counter must be cleared within a period of the overflow time minus 1 source clock
cycle.
8-bit up counter is cleared preferentially and the overflow detection is not executed.
when the 8-bit up counter overflows.
less of the interrupt master enable flag (IMF) setting.
the 8-bit up counter overflows.
Releasing WDCTR<WDTOUT> to "0" causes a watchdog timer interrupt request signal to occur
A watchdog timer interrupt is a non-maskable interrupt, and its request is always accepted, regard-
Setting WDCTR<WDTOUT> to "1" causes a watchdog timer reset request signal to occur when
This watchdog timer reset request signal resets the TMP89FM42 and starts the warm-up operation.
time to half of the overflow time, and allow a watchdog timer reset request signal to occur if a malfunction is
detected.
LD
LD
LD
(WDCTR), 0y00110011
(WDCDR), 0x4E
(WDCDR), 0x4E
Page 77
; WDTWm10, WDTTm01, WDTOUTm1
; Clear the 8-bit up counter
; Clear the 8-bit up counter
20
/fcgck [s], set the counter clear
TMP89FM42