tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 57
tmp89fm42
Manufacturer Part Number
tmp89fm42
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP89FM42.pdf
(408 pages)
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RA001
2.4.4.2
2.4.4.3
2.4.4.4
2.4.4.5
2.4.4.6
2.4.4.7
of the power-on reset circuit, a reset signal is generated and if it is higher than the releasing voltage of the
power-on reset circuit, a reset signal is released.
voltage of the power-on reset circuit, a reset signal is generated.
age has reached a predetermined detection voltage.
is detected.
enable register is set to a combination that puts the CPU into deadlock.
internal circuit is broken down during operation due to noise or other factors.
ison voltage for the power-on reset and the voltage detection circuits.
reset release (tPWUP) and latched into the internal circuit.
that follows reset release is abnormal, IRSTSR<TRMDS> is set to "1".
trimming data need to be reloaded by generating an internal factor reset, such as a system clock reset, and
activating the warm-up operation again.
tion circuit and power-on reset circuit does not satisfy the characteristic specified in the electric character-
istics. Design the system so that the system will not be damaged in such a case.
memory while it is on standby.
Power-on reset
Voltage detection reset
Watchdog timer reset
System clock reset
Trimming data reset
Flash standby reset
The power-on reset is an internal factor reset that occurs when the power is turned on.
When power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage
When power supply voltage goes down, if the supply voltage is equal to or lower than the detecting
Refer to "Power-on Reset circuit".
The voltage detection reset is an internal factor reset that occurs when it is detected that the supply volt-
Refer to "Voltage Detection Circuit".
The watchdog timer reset is an internal factor reset that occurs when an overflow of the watchdog timer
Refer to "Watchdog Timer".
The system clock reset is an internal factor reset that occurs when it is detected that the oscillation
Refer to "Clock Control Circuit".
The trimming data reset is an internal factor reset that occurs when the trimming data latched in the
The trimming data is a data bit provided for adjustment of the ladder resistor that generates the compar-
This bit is loaded from the non-volatile exclusive use memory during the warm-up time that follows
If the trimming data loaded from the non-volatile exclusive use memory during the warm-up operation
When IRSTSR<TRMDS> is read as "1" in the initialize routine immediately after reset release, the
If IRSTSR<TRMDS> is still set to "1" after repeated reading, the detection voltage of the voltage detec-
The flash standby reset is an internal factor reset generated by the reading or writing of data of the flash
Refer to "Flash Memory".
Page 43
TMP89FM42
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