tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 332

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

21.4 Toggle Bit (D6)
21. Flash Memory
RA003
21.5.2 Flash memory control in MCU mode
21.5.2.1 How to write to the flash memory by transferring a control program to the RAM area
using a support program (API) provided inside BOOTROM.
In MCU mode, a write can be performed on the flash memory by executing a control program in RAM or
be executed in RAM must be acquired and stored in the flash memory or it must be imported from an out-
side source through a communication pin. (The following procedure assumes that a program copy is pro-
vided inside the flash memory.)
steps concern the control by a program transferred to RAM. The following procedure is linked with a pro-
gram example to be described later.
This section describes how to execute a control program in RAM in MCU mode. A control program to
Steps 1 through 5 and 11 shown below concern the control by a program in the flash memory, and other
Note 1: Before writing data to the flash memory from the RAM area in MCU mode, the vector area must be
Note 2: Before using a certain interrupt in MCU mode, the vector address corresponding to that interrupt and
1. Set the interrupt master enable flag to "disable (DI)" (IMF m "0").
2. Transfer the write control program to RAM.
3. Establish the nonmaskable interrupt vector in the RAM area.
4. After setting both SYSCR3<RAREA> and SYSCR3<RVCTR> to "1", set "0xD4" on FLSCR4.
5. Invoke the erase processing program in the RAM area by generating a CALL instruction.
6. Set FLSCR1<FLSMD> to "0y101", and specify the area to be erased by making the appropriate
7. Execute the erase command sequence.
8. Perform a read on the same address in the flash memory twice consecutively. (Repeat this step
9. After setting FLSCR1<FLSMD> to "0y010" and FLSCR1<FAREA> to "0y00", set "0xD5" on
10. Generate the RET instruction to return to the flash memory.
11. Invoke the write program in the RAM area by generating a CALL instruction.
12. Set FLSCR1<FLSMD> to "0y101", and make the appropriate FLSCR1<FAREA> setting to
13. Execute the write command sequence.
14. Perform a read on the same address in the flash memory twice consecutively.
15. After setting FLSCR1<FLSMD> to "0y010" and FLSCR1<FAREA> to "0y00", set "0xD5" on
16. Generate the RET instruction to return to the flash memory.
Then allocate RAM to the code area, and switch the vector area to the RAM area.
FLSCR1<FAREA> setting. (Make the appropriate FLSCR1<ROMSEL> setting, as necessary.)
Then set "0xD5" on FLSCR2<CR1EN>.
until the read values become the same.)
FLSCR2<CR1EN>. (This disables the execution of the command sequence and returns FAREA
to the initial state of mapping.)
specify the area (area erased by performing step 7 above) on which a write is to be performed.
(Make the appropriate FLSCR1<ROMSEL> setting, as necessary.) Then set "0xD5" on
FLSCR2<CR1EN>.
(Repeat this step until the read values become the same.)
FLSCR2<CR1EN>. (This disables the execution of the command sequence and returns FAREA
to the initial state of mapping.)
switched to the RAM area by using SYSCR3<RVCTR>, data must be written to the vector addresses
(INTUNDEF, INTSWI: 0x01F8 to 0x01F9, INTWDT: 0x01FC to 0x01FD) that correspond to non-
maskable interrupts, and the interrupt subroutine (RAM area) must be defined. This allows you to trap
the errors that may occur due to an unexpected nonmaskable interrupt during a write. If
SYSCR3<RVCTR> is set in the flash memory area and if an unexpected interrupt occurs during a
write, a malfunction may occur because the vector area in the flash memory cannot be read properly.
the interrupt service routine must be established inside the RAM area. In this case, the nonmaskable
interrupt setting must be made, as explained in Note 1.
Page 318
TMP89FM42