tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 27

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA001
Flash memory control register 1
Flash memory control register 2
(0x0FD0)
(0x0FD1)
FLSCR1
FLSCR2
2.2.2.1
2.2.2.2
2.2.2.3
Note: The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register.
CLR_RAM:
Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This
means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift
register can be checked by reading the register FLSCRM.
Example: RAM initialization program
BAREA
Read/Write
Read/Write
(SFR3) in the data area after reset release.
Bit Symbol
Bit Symbol
After reset
After reset
0x1000 to 0x17FF in the data area. The BOOTROM can be easily written into the Flash by using the Ap-
plication Programming Interface (API) integrated in the BOOTROM.
SFR
RAM
BOOTROM
Note 1: When the BOOTROM is not mapped in the data area, 0xFF is read from 0x1000 to 0x17FF.
Note2: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM
The SFR is mapped to 0x0000 to 0x003F (SFR1), 0x0F00 to 0x0FFF (SFR2) and 0x0E40 to 0x0EFF
Note: Don't access the reserved SFR.
The RAM is mapped to 0x0040 to 0x083F in the data area after reset release.
Note: The contents of the RAM become unstable when the power is turned on and immediately after a reset
The BOOTROM is not mapped in the code area or the data area after reset release.
Setting FLSMD<BAREA> to "1" maps the BOOTROM to 0x1000 to 0x17FF in the code area and to
is released. To execute the program by using the RAM, transfer the program to be executed in the ini-
tialization routine.
LD
LD
LD
LD
INC
DEC
JRS
Specifies mapping of the
BOOTROM in the code and data
areas
mode.
7
0
7
*
HL, RAM_TOP_ADDRESS
A, 0x00
BC, BYTE_OF_CLEAR_BYTES
(HL), A
HL
BC
F, CLR_RAM
(FLSMD)
R/W
6
1
6
*
5
0
5
*
Page 13
0 :
1 :
The BOOTROM is not mapped to 0x1000 to 0x17FF in the code area and
to 0x1000 to 0x17FF in the data area.
The BOOTROM is mapped to 0x1000 to 0x17FF in the code area and to
0x1000 to 0x17FF in the data area.
BAREA
; Head of address of the RAM to be initialized
; Initialization data
; Number of bytes of RAM to be initialized -1
; Initialization of the RAM
; Initialization address increment
; Have all the RAMs been initialized?
R/W
4
0
4
*
CR1EN
W
3
0
3
*
(FAREA)
R/W
2
0
2
*
1
1
0
*
(ROMSEL)
R/W
TMP89FM42
0
0
0
*