tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 200

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14. 8-bit Timer Counter (TC0)
RA002
(Example)
14.4.4.2 Operation
14.4.4.3 Double buffer
clock. When a match between the internal up counter value and the value set to T00PWM is detected, the
output of the
"H" level. When T00MOD<TFF0> is "1", the
T00REG is detected, the output of the
PPG0
the "L" to "H" level. At this time, an INTT00 interrupt request is generated.
"0x00". The
buffer is disabled by setting T00MOD<DBE0> to "0" or enabled by setting T00MOD<DBE0> to "1".
Setting T001CR<T00RUN> to "1" allows the up counter to increment based on the selected source
Subsequently, the up counter continues counting up. When a match between the up counter value and
When T001CR<T00RUN> is set to "0" during the operation, the up counter is stopped and cleared to
The double buffer can be used for T00PWM and T00REG by setting T00MOD<DBE0>. The double
• When the double buffer is enabled
• When the double buffer is disabled
pin changes from the "H" to "L" level. When T00MOD<TFF0> is "1", the
Operate TC00 in the 8-bit PPG mode with the operation clock of fcgck/2 and output the 8Ps duty pulse in 32Ps cycles (fcgck
= 10 MHz)
SET
SET
LD
DI
SET
EI
LD
LD
set value is first stored in the double buffer, and T00PWM (T00REG) is not updated immedi-
ately. T00PWM (T00REG) compares the previous set value with the up counter value. When
an INTT00 interrupt request is generated, the double buffer set value is stored in T00PWM
(T00REG). Subsequently, the match detection is executed using a new set value.
(the last set value) is read out, not the T00PWM (T00REG) value (the currently effective
value).
set value is immediately stored in both the double buffer and T00PWM (T00REG).
set value is immediately stored in T00PWM (T00REG). Subsequently, the match detection is
executed using a new set value. If the value set to T00PWM (T00REG) is smaller than the up
counter value, the
is executed using a new set value. If the value set to T00PWM (T00REG) is equal to the up
counter value, the match detection is executed immediately after data is written into T00PWM
(T00REG). Therefore, the timing of changing the
the source clock (Figure 14-10). If these are problems, enable the double buffer.
set value is immediately stored in T00PWM (T00REG).
When a write instruction is executed on T00PWM (T00REG) during the timer operation, the
When a read instruction is executed on T00PWM (T00REG), the value in the double buffer
When a write instruction is executed on T00PWM (T00REG) while the timer is stopped, the
When a write instruction is executed on T00PWM (T00REG) during the timer operation, the
When a write instruction is executed on T00PWM (T00REG) while the timer is stopped, the
PPG0
PPG0
pin returns to the level selected at T00MOD<TFF0>.
pin is reversed. When T00MOD<TFF0> is "0", the
(P7FC).0
(P7CR).0
(POFFCR0),0x10
(EIRH).4
(T00MOD),0xF3
(T00REG),0xA0
PPG0
pin is not reversed until the up counter overflows and a match detection
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PPG0
; Sets P7FC0 to "1"
; Sets P7CR0 to "1"
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects the 8-bit PPG mode and fcgck/2
; Sets the timer register (cycle)
; 32Ps / (2/fcgck) = 0xA0
pin is reversed again. When T00MOD<TFF0> is "0", the
PPG0
pin changes from the "H" to "L" level.
PPG0
pin may not be an integral multiple of
PPG0
pin changes from the "L" to
PPG0
pin changes from
TMP89FM42