at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 132
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at91rm3400
Manufacturer Part Number
at91rm3400
Description
Atmel Advanced At91 Arm Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.AT91RM3400.pdf
(461 pages)
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Divider and PLL Blocks
PLL Filters
132
AT91RM3400
The Clock Generator features two Divider/PLL Blocks that generates a wide range of
frequencies. Additionally, they provide a 48 MHz signal to the embedded USB device
and/or host ports, regardless of the frequency of the Main Clock.
Figure 40 shows the block diagram of the divider and PLL blocks.
Figure 40. Divider and PLL Blocks Block Diagram
The two PLLs require connection to an external second-order filter through the pins
PLLRC. Figure 41 shows a schematic of these filters.
Figure 41. PLL Capacitors and Resistors
Values of R, C1 and C2 to be connected to the PLLRC pins must be calculated as a
function of the PLL input frequency, the PLL output frequency and the phase margin. A
trade-off has to be found between output signal overshoot and startup time.
Main
Clock
Slow
Clock
C2
Divider A
Divider B
DIVB
DIVA
C1
R
PLLRCB
PLLRCA
PLLRC
GND
MULB
MULA
PLLBCOUNT
PLLACOUNT
Counter
Counter
PLL B
PLL A
PLL A
PLL B
OUTB
OUTA
PLL
LOCKB
LOCKA
PLL A
Output
PLL B
Output
1790A–ATARM–11/03
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