at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 185

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Receiver Ready
Receiver Overrun
Parity Error
1790A–ATARM–11/03
Figure 57. Character Reception
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY
status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when
the receive holding register DBGU_RHR is read.
Figure 58. Receiver Ready
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the
last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in
DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR
with the bit RSTSTA (Reset Status) at 1.
Figure 59. Receiver Overrun
Each time a character is received, the receiver calculates the parity of the received data bits,
in accordance with the field PAR in DBGU_MR. It then compares the result with the received
parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the
RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the
bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status com-
mand is written, the PARE bit remains at 1.
Figure 60. Parity Error
Example: 8-bit, parity enabled 1 stop
Sampling
RXRDY
RXRDY
RXRDY
OVRE
DRXD
DRXD
PARE
DRXD
DRXD
S
S
S
0.5 bit
period
D0
D0
D0
True Start Detection
D1
D1
D1
period
D2
1 bit
D2
D2
D3
D3
D0
D3
D4
D4
D1
D5
D5
D4
D6
D6
D5
D2
D7
D7
D6
P
P
Wrong Parity Bit
D7
D3
stop
P
S
S
stop
D4
Read DBGU_RHR
D0
D0
D1
D1
D5
D2
D2
D3
D3
D6
RSTSTA
D4
D4
AT91RM3400
D5
D5
D7
D6
D6
Parity Bit
D7
D7
P
P
stop
Stop Bit
RSTSTA
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