at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 157

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Watchdog Timer
(WDT)
Real-time Timer
(RTT)
1790A–ATARM–11/03
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped
in a deadlock. It is built around a 16-bit down counter loaded with the value defined in
ST_WDMR (Watchdog Mode Register).
At reset, the value of the ST_WDMR is 0x00020000, corresponding to the maximum value of
the counter. The watchdog overflow signal is tied low during 8 slow clock cycles when a
watchdog overflow occurs (EXTEN bit set in ST_WDMR).
It uses the Slow Clock divided by 128 to establish the maximum watchdog period to be 256
seconds (with a typical slow clock of 32.768 kHz).
In normal operation, the user reloads the Watchdog at regular intervals before the timer over-
flow occurs, by setting the bit WDRST in the ST_CR (Control Register).
If an overflow does occur, the watchdog timer:
•
•
•
•
Writing the ST_WDMR does not reload or restart the down counter. When the ST_CR is writ-
ten the watchdog counter is immediately reloaded from ST_WDMR and restarted and the
Slow Clock 128 divider is also immediately reset and restarted.
Figure 50. Watchdog Timer
The Real-Time Timer is used to count elapsed seconds. It is built around a 20-bit counter fed
by Slow Clock divided by a programmable value. At reset, this value is set to 0x8000, corre-
sponding to feeding the real-time counter with a 1 Hz signal when the Slow Clock is 32.768
Hz. The 20-bit counter can count up to 1048576 seconds, corresponding to more than 12
days, then roll over to 0.
The Real-Time Timer value can be read at any time in the register ST_CRTR (Current Real-
time Register). As this value can be updated asynchronously to the master clock, it is advis-
able to read this register twice at the same value to improve accuracy of the returned value.
This current value of the counter is compared with the value written in the alarm register
ST_RTAR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in
TC_SR is set. The alarm register is set to its maximum value, corresponding to 0, after a reset.
The bit RTTINC in ST_SR is set each time the 20-bit counter is incremented. This bit can be
used to start an interrupt, or generate a one-second signal.
Sets the WDOVF bit in ST_SR (Status Register), from which an interrupt can be
generated.
Generates a pulse for 8 slow clock cycles on the external signal watchdog overflow if the
bit EXTEN in ST_WDMR is set.
Generates an internal reset if the parameter RSTEN in ST_WDMR is set.
Reloads and restarts the down counter.
SLCK
1/128
16-bit Down
WDRST
Counter
WV
RSTEN
EXTEN
AT91RM3400
WDOVF Status
Internal Reset
NWDOVF
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