at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 314
at91rm3400
Manufacturer Part Number
at91rm3400
Description
Atmel Advanced At91 Arm Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.AT91RM3400.pdf
(461 pages)
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Functional
Description
Figure 122. SSC Functional Block Diagram
314
AT91RM3400
APB
MCK
PDC
Divider
Interface
Clock
User
This chapter contains the functional description of the following: SSC Functional Block, Clock
Management, Data format, Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by
programming the receiver to use the transmit clock and/or to start a data transfer when trans-
mission starts. Alternatively, this can be done by programming the transmitter to use the
receive clock and/or to start a data transfer when reception starts. The transmitter and the
receiver can be programmed to operate with the clock signals provided on either the TK or RK
pins. This allows the SSC to support many slave-mode data transfers. The maximum clock
speed allowed on the TK and RK pins is the master clock divided by 2. Each level of the clock
must be stable for at least two master clock periods.
Interrupt Control
AIC
TF
RF
TX Clock
RF
TF
TK Input
RK Input
RX clock
Selector
Selector
Start
Start
RX PDC
TX PDC
Load Shift
Load Shift
Transmitter
Transmit Clock
Receive Clock
Controller
Controller
Receiver
Transmit Holding
Receive Holding
Register
Register
Transmit Shift Register
Receive Shift Register
RX Clock
TX clock
Holding Register
Holding Register
Transmit Sync
Receive Sync
Clock Output
Clock Output
Frame Sync
Frame Sync
Controller
Controller
Controller
Controller
1790A–ATARM–11/03
TK
RK
TF
TD
RD
RF
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