at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 133

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

PLL Source Clock
Divider and Phase Lock Loop
Programming
PLLB Divider by 2
Clock Controllers
Master Clock Controller
1790A–ATARM–11/03
The source of PLLs A and B is respectively the output of Divider A, i.e., the Main Clock
divided by DIVA, and the output of Divider B, i.e., the Main Clock divided by DIVB.
As the input frequency of the PLLs is limited, the user has to make sure that the pro-
gramming of DIVA and DIVB are compliant with the input frequency range of the PLLs,
which is given in the section “DC Characteristics” on page 432.
The two dividers increase the accuracy of the PLLA and the PLLB clocks independently
of the input frequency.
The Main Clock can be divided by programming the DIVB field in CKGR_PLLBR and
the DIVA field in CKGR_PLLAR. Each divider can be set between 1 and 255 in steps of
1. When the DIVA and DIVB fields are set to 0, the output of the divider and the PLL out-
puts A and B are a continuous signal at level 0. On reset, the DIVA and DIVB fields are
set to 0, thus both PLL input clocks are set to 0.
The two PLLs of the clock generator allow multiplication of the divider’s outputs. The
PLLA and the PLLB clock signals have a frequency that depends on the respective
source signal frequency and on the parameters DIV (DIVA, DIVB) and MUL (MULA,
MULB). The factor applied to the source signal frequency is (MUL + 1)/DIV. When
MULA or MULB is written to 0, the corresponding PLL is disabled and its power con-
sumption is saved. Re-enabling the PLLA or the PLLB can be performed by writing a
value higher than 0 in the MULA or MULB field, respectively.
Whenever a PLL is re-enabled or one of its parameters is changed, the LOCKA or
LOCKB bit in PMC_SR is automatically cleared. The values written in the PLLACOUNT
or PLLBCOUNT fields in CKGR_PPLAR and CKGR_PLLBR, respectively, are loaded in
the corresponding PLL counter. The PLL counter then decrements at the speed of the
Slow Clock until it reaches 0. At this time, the corresponding LOCK bit is set in PMC_SR
and can trigger an interrupt to the processor. The user has to load the number of Slow
Clock cycles required to cover the PLL transient time into the PLLACOUNT and PLLB-
COUNT field. The transient time depends on the PLL filters. The initial state of the PLL
and its target frequency can be calculated using a specific tool provided by Atmel.
In ARM9-based systems, the PLLB clock may be divided by two. This divider can be
enabled by setting the bit USB_96M of CKGR_PLLBR. In this case, the divider by 2 is
enabled and the PLLB must be programmed to output 96 MHz and not 48 MHz, thus
ensuring correct operation of the USB bus.
The Power Management Controller provides the clocks to the different peripherals of the
system, either internal or external. It embeds the following elements:
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The Master Clock Controller provides selection and division of the Master Clock (MCK).
MCK is the clock provided to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator.
Selecting the Slow Clock enables Slow Clock Mode by providing a 32.768 kHz signal to
the whole device. Selecting the Main Clock saves power consumption of both PLLs, but
the Master Clock Controller, that selects the Master Clock.
the Processor Clock Controller, that implements the Idle Mode.
the Peripheral Clock Controller, that provides power saving by controlling clocks of
the embedded peripherals.
the USB Clock Controller, that distributes the 48 MHz clock to the USB controllers.
the Programmable Clock Controller, that allows generation of up to four
programmable clock signals on external pins.
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