at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 135

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Peripheral Clock Controller
USB Clock Controller
USB Device Clock Control
USB Device Port Suspend
USB Host Clock Control
Programmable Clock Output
Controller
1790A–ATARM–11/03
When the Processor Clock is disabled, the current instruction is finished before the clock
is stopped, but this does not prevent data transfers from other masters of the system
bus.
The PMC controls the clocks of each embedded peripheral. The user can individually
enable and disable the Master Clock on the peripherals by writing into the Peripheral
Clock Enable (PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The
status of the peripheral clock activity can be read in the Peripheral Clock Status Register
(PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. When the clock is
re-enabled, the peripheral resumes action where it left off. The peripheral clocks are
automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the
peripheral has executed its last programmed operation before disabling the clock. This
is to avoid data corruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER,
PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level.
Generally, the bit number corresponds to the interrupt source number assigned to the
peripheral.
If using one of the USB ports, the user has to program the Divider and PLL B block to
output a 48 MHz signal with an accuracy of ± 0.25%.
When the clock for the USB is stable, the USB device and host clocks, UDPCK and
UHPCK, can be enabled. They can be disabled when the USB transactions are finished,
so that the power consumption generated by the 48 MHz signal on these peripherals is
saved.
The USB ports require both the 48 MHz signal and the Master Clock. The Master Clock
may be controlled via the Peripheral Clock Controller.
The USB Device Port clock UDPCK can be enabled by writing 1 at the UDP bit in
PMC_SCER (System Clock Enable Register) and disabled by writing 1 at the bit UDP in
PMC_SCDR (System Clock Disable Register). The activity of UDPCK is shown in the bit
UDP of PMC_SCSR (System Clock Status Register).
When the USB Device Port detects a suspend condition, the 48 MHz clock is automati-
cally disabled, i.e., the UDP bit in PMC_SCSR is cleared. It is also possible to
automatically disable the Master Clock provided to the USB Device Port on a suspend
condition. The MCKUDP bit in PMC_SCSR configures this feature and can be set or
cleared by writing one in the same bit of PMC_SCER and PMC_SCDR.
The USB Host Port clock UHPCK can be enabled by writing 1 at the UHP bit in
PMC_SCER (System Clock Enable Register) and disabled by writing 1 at the UHP bit in
PMC_SCDR (System Clock Disable Register). The activity of UDPCK is shown in the bit
UHP of PMC_SCSR (System Clock Status Register).
The PMC controls up to four signals to be output on external pins PCK0 to PCK3. Each
signal can be independently programmed via the registers PMC_PCK0 to PMC_PCK3.
PCK0 to PCK3 can be independently selected between the four clocks provided by the
Clock Generator by writing the CSS field in PMC_PCK0 to PMC_PCK3. Each output
signal can also be divided by a power of 2 between 1 and 64 by writing the field PRES
(Prescaler) in PMC_PCK0 to PMC_PCK3.
AT91RM3400
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