r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 12

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

6.4
6.5
6.6
6.7
Rev. 1.00 Sep. 19, 2008 Page xii of xxx
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10 DRAM Access Control Register (DRACCR)....................................................... 177
6.3.11 Refresh Control Register (REFCR) ...................................................................... 180
6.3.12 Refresh Timer Counter (RTCNT)......................................................................... 183
6.3.13 Refresh Time Constant Register (RTCOR) .......................................................... 183
Bus Control........................................................................................................................ 184
6.4.1
6.4.2
6.4.3
6.4.4
Basic Bus Interface ............................................................................................................ 190
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
Address/Data Multiplexed I/O Interface............................................................................ 204
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
DRAM Interface ................................................................................................................ 218
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.7.8
6.7.9
Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 165
Bus Control Register (BCR) ................................................................................. 166
Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 168
DRAM Control Register (DRAMCR) .................................................................. 169
Area Division........................................................................................................ 184
Bus Specifications ................................................................................................ 185
Memory Interfaces................................................................................................ 187
Chip Select Signals ............................................................................................... 189
Data Size and Data Alignment.............................................................................. 190
Valid Strobes ........................................................................................................ 191
Basic Timing......................................................................................................... 192
Wait Control ......................................................................................................... 200
Read Strobe (RD) Timing..................................................................................... 201
Extension of Chip Select (CS) Assertion Period................................................... 203
Setting Address/Data Multiplexed I/O Space ....................................................... 204
Address/Data Multiplexing................................................................................... 204
Data Bus ............................................................................................................... 205
Address Hold Signal ............................................................................................. 205
Basic Timing......................................................................................................... 205
Wait Control ......................................................................................................... 214
Read Strobe (RD) Timing..................................................................................... 215
Extension of Chip Select (CS) Assertion Period in Data Cycle............................ 216
Setting DRAM Space............................................................................................ 218
Address Multiplexing ........................................................................................... 218
Data Bus ............................................................................................................... 219
Pins Used for DRAM Interface............................................................................. 220
Basic Timing......................................................................................................... 221
Column Address Output Cycle Control ................................................................ 222
Row Address Output State Control....................................................................... 223
Precharge State Control ........................................................................................ 226
Wait Control ......................................................................................................... 227