r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 463

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

(5)
Figure 8.20 shows an example of normal mode transfer activated by the EDREQ pin low level.
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
Figure 8.21 shows an example of block transfer mode transfer activated by the EDREQ pin low
level.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of write cycle.
φ
EDREQ
Address bus
DMA control
Channel
Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level
EDREQ Pin Low Level Activation Timing
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Idle
[1]
Minimum 3 cycles
Request
Bus release
[2]
Read
[3]
Request clearance period
Transfer source
DMA read
Write
DMA write
destination
Transfer
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
Rev. 1.00 Sep. 19, 2008 Page 433 of 1342
[5]
Section 8 EXDMA Controller (EXDMAC)
Read
Request clearance period
[6]
Transfer source
DMA read
Write
DMA write
destination
Transfer
Idle
REJ09B0467-0100
Acceptance
resumed
[7]
Bus release