r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 313

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Bus Controller (BSC)
(5)
Idle Cycle in Case of DRAM Space Access after Normal Space Access
In a DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1,
ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas,
for example, if the second read is a full access to DRAM space, only a T
cycle is inserted, and a
p
T
cycle is not. The timing in this case is shown in figure 6.81.
i
External read
DRAM space read
T
T
T
T
T
T
T
1
2
3
p
r
c1
c2
φ
Address bus
RD
Data bus
Figure 6.81 Example of DRAM Full Access after External Read
(CAST = 0)
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. The timing in this case is illustrated in figures 6.82 and 6.83.
Rev. 1.00 Sep. 19, 2008 Page 283 of 1342
REJ09B0467-0100