r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 365
r4f2456
Manufacturer Part Number
r4f2456
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R4F2456.pdf
(1376 pages)
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Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt
request, and reactivating channel 0A. The address register and count register areas are set again
during the first DTC transfer, then the control register area is set again during the second DTC
chain transfer. When re-setting the control register area, perform masking by setting bits in
DMAWER to prevent modification of the contents of other channels.
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)
DTC
First transfer area
Second transfer area
using chain transfer
DMACR_0A
DMACR_1A
DMAWER
Rev. 1.00 Sep. 19, 2008 Page 335 of 1342
MAR_0AH
MAR_0BH
MAR_1AH
MAR_1BH
MAR_0AL
MAR_0BL
MAR_1AL
MAR_1BL
ETCR_0A
ETCR_0B
ETCR_1A
ETCR_1B
IOAR_0A
IOAR_0B
IOAR_1A
IOAR_1B
DMABCR
Section 7 DMA Controller (DMAC)
DMACR_0B
DMACR_1B
DMATCR
REJ09B0467-0100
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