r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 13

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

6.8
6.9
6.10 Idle Cycle........................................................................................................................... 279
6.11 Write Data Buffer Function ............................................................................................... 299
6.12 Bus Release........................................................................................................................ 300
6.13 Bus Arbitration .................................................................................................................. 304
6.14 Bus Controller Operation in Reset ..................................................................................... 307
6.15 Usage Notes ....................................................................................................................... 307
6.7.10 Byte Access Control ............................................................................................. 230
6.7.11 Burst Operation..................................................................................................... 231
6.7.12 Refresh Control..................................................................................................... 236
6.7.13 DMAC and EXDMAC Single Address Transfer Mode and
Synchronous DRAM Interface........................................................................................... 245
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.8.7
6.8.8
6.8.9
6.8.10 Bus Cycle Control in Write Cycle ........................................................................ 256
6.8.11 Byte Access Control ............................................................................................. 257
6.8.12 Burst Operation..................................................................................................... 260
6.8.13 Refresh Control..................................................................................................... 263
6.8.14 Mode Register Setting of Synchronous DRAM.................................................... 270
6.8.15 DMAC and EXDMAC Single Address Transfer Mode and
Burst ROM Interface.......................................................................................................... 276
6.9.1
6.9.2
6.9.3
6.10.1 Operation .............................................................................................................. 279
6.10.2 Pin States in Idle Cycle......................................................................................... 298
6.12.1 Operation .............................................................................................................. 300
6.12.2 Pin States in External Bus Released State ............................................................ 301
6.12.3 Transition Timing ................................................................................................. 302
6.13.1 Operation .............................................................................................................. 304
6.13.2 Bus Transfer Timing............................................................................................. 305
6.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 307
DRAM Interface ................................................................................................... 242
Setting Continuous Synchronous DRAM Space................................................... 245
Address Multiplexing ........................................................................................... 246
Data Bus ............................................................................................................... 247
Pins Used for Synchronous DRAM Interface....................................................... 247
Synchronous DRAM Clock .................................................................................. 249
Basic Timing......................................................................................................... 249
CAS Latency Control............................................................................................ 251
Row Address Output State Control....................................................................... 253
Precharge State Count........................................................................................... 254
Synchronous DRAM Interface ............................................................................. 271
Basic Timing......................................................................................................... 276
Wait Control ......................................................................................................... 278
Write Access......................................................................................................... 278
Rev. 1.00 Sep. 19, 2008 Page xiii of xxx