r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 219

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

6.4.4
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7
signals output timing.
Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit
for the port corresponding to the CS0 to CS7 pins.
In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a
reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits
and PFCR0 bits should be set to 1 when outputting signals CS1 to CS7.
In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state
after a reset and so the corresponding DDR bits and PFCR0 bits should be set to 1 when
outputting signals CS0 to CS7.
When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals.
When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2456R
Group, outputs CS2, CS3, CS4, and CS5 are used as RAS, CAS, WE, and CLK signals.
Note: The A23E bit in PFCR1 should be cleared to 0 when CS7 signal is output in the H8S/2454
Group.
Chip Select Signals
φ
Address bus
CSn
Figure 6.7 CSn Signal Output Timing (n = 0 to 7)
T
1
Area n external address
Bus cycle
T
2
Rev. 1.00 Sep. 19, 2008 Page 189 of 1342
T
3
Section 6 Bus Controller (BSC)
REJ09B0467-0100