r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 14

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 DMA Controller (DMAC).................................................................309
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Rev. 1.00 Sep. 19, 2008 Page xiv of xxx
6.15.2 External Bus Release Function and Software Standby ......................................... 307
6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 307
6.15.4 BREQO Output Timing ........................................................................................ 308
6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 308
Features.............................................................................................................................. 309
Input/Output Pins............................................................................................................... 311
Register Descriptions ......................................................................................................... 311
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Activation Sources............................................................................................................. 337
7.4.1
7.4.2
7.4.3
Operation ........................................................................................................................... 339
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles ............................................. 372
7.5.11 Write Data Buffer Function .................................................................................. 378
7.5.12 Multi-Channel Operation...................................................................................... 379
7.5.13 Relation between DMAC and External Bus Requests,
7.5.14 DMAC and NMI Interrupts .................................................................................. 382
7.5.15 Forced Termination of DMAC Operation ............................................................ 383
7.5.16 Clearing Full Address Mode................................................................................. 384
Interrupt Sources................................................................................................................ 385
Usage Notes ....................................................................................................................... 386
Memory Address Registers (MARA and MARB)................................................ 313
I/O Address Registers (IOARA and IOARB)....................................................... 313
Execute Transfer Count Registers (ETCRA and ETCRB) ................................... 314
DMA Control Registers (DMACRA and DMACRB) .......................................... 315
DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 323
DMA Write Enable Register (DMAWER)........................................................... 334
DMA Terminal Control Register (DMATCR) ..................................................... 336
Activation by Internal Interrupt Request .............................................................. 338
Activation by External Request ............................................................................ 339
Activation by Auto-Request ................................................................................. 339
Transfer Modes..................................................................................................... 339
Sequential Mode ................................................................................................... 342
Idle Mode.............................................................................................................. 344
Repeat Mode......................................................................................................... 347
Single Address Mode............................................................................................ 351
Normal Mode........................................................................................................ 354
Block Transfer Mode ............................................................................................ 357
Basic Bus Cycles .................................................................................................. 363
DMA Transfer (Dual Address Mode) Bus Cycles................................................ 364
Refresh Cycles, and EXDMAC ........................................................................... 381