r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 247
r4f2456
Manufacturer Part Number
r4f2456
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R4F2456.pdf
(1376 pages)
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When consecutively reading from the same area connected to a peripheral LSI whose output
floating time is long, data outputs from the peripheral LSI may conflict with address outputs from
this LSI. The data conflict can be avoided by inserting the CS assertion period extension cycle
after the access cycle. Figure 6.32 shows an example of the operation. In the figure, both bus
cycles A and B are read access cycles to the same area which is address/data multiplexed I/O
space. (a) shows an example of conflict occurring between data outputs from the peripheral LSI
whose output floating time is long and address outputs from this LSI because the CS assertion
period extension cycle is not inserted. (b) shows an example of the data conflict being avoided by
inserting the CS assertion period extension cycle.
Address bus
Data bus
WR
CS
RD
φ
(a) Without CS assertion period extension cycle
(CSXTn = 0)
Bus cycle A
Figure 6.32 Consecutive Read Accesses to Same Area
Output floating
time is long
(Address/Data Multiplexed I/O Space)
Bus cycle B
Data conflict
Address bus
Data bus
WR
RD
CS
φ
Rev. 1.00 Sep. 19, 2008 Page 217 of 1342
Bus cycle A
(b) With CS assertion period extension cycle
(CSXTn = 1)
Section 6 Bus Controller (BSC)
Bus cycle B
REJ09B0467-0100
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