m52d128168a Elite Semiconductor Memory Technology Inc., m52d128168a Datasheet

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m52d128168a

Manufacturer Part Number
m52d128168a
Description
2m X 16 Bit X 4 Banks Mobile Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
ESMT
Mobile SDRAM
FEATURES
GENERAL DESCRIPTION
words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT (Top View)
Elite Semiconductor Memory Technology Inc.
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
- PASR (Partial Array Self Refresh)
- TCSR (Temperature Compensated Self Refresh)
- DS (Driver Strength)
1.8V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
EMRS cycle with address
All inputs are sampled at the positive going edge of the
system clock
Special function support
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
The M52D128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152
A
LDQM
10
V
V
V
V
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CAS
RAS
BA0
BA1
V
DDQ
V
V
DDQ
SSQ
SSQ
WE
/AP
CS
DD
DD
A
A
A
A
DD
0
1
2
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DQ15
V
DQ14
DQ13
V
DQ12
DQ11
V
DQ10
DQ9
V
DQ8
V
NC
UDQM
CLK
CKE
NC
A
A
A
A
A
A
A
V
SS
SSQ
DDQ
SSQ
DDQ
SS
11
9
8
7
6
5
4
SS
A
B
C
D
E
F
G
H
J
UDQM
DQ12
VSS
DQ14
DQ10
DQ8
VSS
NC
1
A8
ORDERING INFORMATION
M52D128168A-7TG
M52D128168A-7BG
M52D128168A-7.5TG 133MHz
M52D128168A-7.5BG 133MHz
M52D128168A-10TG
M52D128168A-10BG
DQ15
DQ13
DQ11
DQ9
CLK
NC
A11
A5
A7
2
Product ID
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
3
A4
4
2M x 16 Bit x 4 Banks
Mobile Synchronous DRAM
5
Max Freq.
143MHz
143MHz
100MHz
100MHz
6
Publication Date: Aug. 2009
Revision: 1.3
VDDQ
VSSQ
VDDQ
VSSQ
M52D128168A
VDD
CAS
BA0
7
A0
A3
54 Ball FBGA
54 Ball FBGA
54 Ball FBGA
LDQM
DQ0
DQ2
DQ4
DQ6
RAS
BA1
54 TSOP II
54 TSOP II
54 TSOP II
A1
A2
8
Package
VDD
DQ1
DQ3
DQ7
DQ5
VDD
A10
WE
CS
9
Comments
(mm ball pitch)
54 Ball FBGA
(8x8mm)
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
1/48

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m52d128168a Summary of contents

Page 1

... GENERAL DESCRIPTION The M52D128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized 2,097,152 words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications ...

Page 2

... Data inputs / outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. M52D128168A Bank D Bank C Bank B Bank A ...

Page 3

... ≤ 3ns acceptable. ≤ 3ns acceptable all other pins are not under test = 0V. DDQ ≤ OUT DDQ = 25 C ° 1MHz) SYMBOL C IN1 C IN2 C OUT M52D128168A VALUE -1.0 ~ 2.6 -1.0 ~ 2.6 -55 ~ +150 ° ) MAX UNIT 1 +0.3 V DDQ 0 0.2 V μ μ ...

Page 4

... IL CC Input signals are stable I = 0mA, Page Burst OL All Band Activated (min) CCD CCD ≥ (min) RFC RFC TCSR range 4 Banks ≤ CKE 0.2V 2 Bank 1 Bank ≤ CKE 0.2V M52D128168A Version -7 -7 0.5 ∞ = 0.5 =10ns 10 ∞ ∞ =15ns 25 ∞ ...

Page 5

... RFC t (min) CDL t (min) RDL t (min) BDL t (min) CCD t (min) MRD t (max) REF CAS latency=3 CAS latency=2 after self refresh exit. RFC M52D128168A ° ) Unit / 0 DDQ ns V DDQ Vtt =0.5x VDDQ 50 Z0= (Fig.2) AC Output Load Circuit Version Unit -7.5 - ...

Page 6

... CC 9 6.5 t SAC 8 t 2.5 2 2.5 2 2.5 2 SLZ 6.5 t SHZ 8 *All AC parameters are measured from half to half. M52D128168A -7.5 -10 Max Min Max 10 1000 1000 2 1 Publication Date: Aug. 2009 Revision: 1.3 Unit Note ...

Page 7

... Valid Don’t Care Logic High Logic Low) after the end of burst. RP M52D128168A A11, DQM BA0 WE A10/AP A9~A0 BA1 CODE Row Address L Column ...

Page 8

... Reserved Reserved Reserved Reserved Reserved Reserved M52D128168A Burst Length Burst Length Type Sequential Interleave Reserved Reserved ...

Page 9

... If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored has +/-5°C tolerance Elite Semiconductor Memory Technology Inc PASR M52D128168A Address bus Extended Mode Register Set A2-A0 Self Refresh Coverage 000 4Bank 2 Bank (BankA& BankB) or 001 (BA1=0) 1 Bank (BankA) or 010 ...

Page 10

... M52D128168A Interleave Interleave ...

Page 11

... A10~A11 and BA1~BA0. The write burst length is programmed using A9. A7~A8, A10/AP~A11 and BA0~BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies. are high, The SDRAM M52D128168A Publication Date: Aug. 2009 Revision: 1.3 11/48 ...

Page 12

... At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. M52D128168A after the last data input to RDL is defined as the minimum number of clock ...

Page 13

... NOP’s for a minimum time of t RAS reaches idle state to begin normal operation. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. with clock cycle RFC M52D128168A before the SDRAM RFC Publication Date: Aug. 2009 Revision: 1.3 13/48 ...

Page 14

... The DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA1 and BA0 (BS) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM’s RAS falling. Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 14/48 ...

Page 15

... Read command ( CS , CAS = Low, RAS , WE = High) Read data is available after CAS latency requirements have been met. This command sets the burst start address given by the column address. Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 15/48 ...

Page 16

... Before executing self refresh, all banks must be precharged. Burst stop command ( Low, RAS , CAS = High) This command terminates the current burst operation. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 16/48 ...

Page 17

... No operation ( CS = Low , RAS , CAS , WE = High) This command is not an execution command. No operations begin or terminate by this command. Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 17/48 ...

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... M52D128168A ...

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... M52D128168A ...

Page 20

... D Q Elite Semiconductor Memory Technology Inc M52D128168A D 3 Publication Date: Aug. 2009 Revision: 1.3 20/48 ...

Page 21

... M52D128168A Publication Date: Aug. 2009 Revision: 1.3 21/48 ...

Page 22

... M52D128168A ...

Page 23

... determinates the last data write. RDL min delay) with DQM. RAS M52D128168A * ...

Page 24

... from self refresh exit command, any other command can not be accepted. RFC M52D128168A ...

Page 25

... During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 25/48 ...

Page 26

... NOP (Continue Burst to End ILLEGAL X BA CA, A10/AP ILLEGAL X BA RA, RA10 ILLEGAL ILLEGAL M52D128168A ACTION Row Active) Row Active) Row active Row Active) Row Active) Row active Row Active) Row Active) Row Active) Row Active) Publication Date: Aug. 2009 Revision: 1.3 Note 2 2 ...

Page 27

... X X NOP ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address M52D128168A ACTION Idle after t RP Idle after t RP Idle after t RP Row Active after t RCD Row Active after t RCD Idle after t RFC Idle after t RFC Idle after 2clocks Idle after 2clocks AP = Auto Precharge Publication Date: Aug ...

Page 28

... X X Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend must be satisfy before any command other than exit. SS M52D128168A ACTION Note Idle after tRFC (ABI) 6 Idle after tRFC (ABI) 6 ABI 7 ABI Publication Date: Aug ...

Page 29

... ESMT Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3, Burst Length = 1 Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 29/48 ...

Page 30

... Enable auto precharge, precharge bank B at end of burst. 0 Enable auto precharge, precharge bank C at end of burst. 1 Enable auto precharge, precharge bank D at end of burst. BA0 Precharge 0 Bank A 1 Bank B 0 Bank C 1 Bank D X All Banks M52D128168A Operating Publication Date: Aug. 2009 Revision: 1.3 30/48 ...

Page 31

... Issue mode register set command to initialize the mode register. 7. Issue extended mode register set command to set PASR and DS. Elite Semiconductor Memory Technology Inc M52D128168A ...

Page 32

... Precharge Row Active ( A - Bank ) ( A - Bank ) ) after the clock. SHZ M52D128168A ...

Page 33

... Row precharge will interrupt writing. Last data input DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc. M52D128168A before row precharge, will be written. RDL Publication Date: Aug. 2009 Revision: 1 ...

Page 34

... Note can be don’t cared when RAS , CAS and WE are high at the clock high going edge interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 ...

Page 35

... To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data interrupt burst write by Row precharge, both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 35/48 ...

Page 36

... ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 *Note should be met to complete write. CDL Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 36/48 ...

Page 37

... ESMT Read & Write cycle with Auto Precharge @ Burst Length = 4 *Note should be controlled to meet minimum t CDL (In the case of Burst Length = 1 & 2) Elite Semiconductor Memory Technology Inc. before internal precharge start. RAS M52D128168A Publication Date: Aug. 2009 Revision: 1.3 37/48 ...

Page 38

... ESMT Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4 *Note: 1. DQM is needed to prevent bus contention Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 38/48 ...

Page 39

... Both cases are illustrated above timing diagram. See the label them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycles”. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 39/48 ...

Page 40

... DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 40/48 ...

Page 41

... All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + t 3. Can not violate minimum refresh specification. (64ms) Elite Semiconductor Memory Technology Inc. prior to Row active command. SS M52D128168A Publication Date: Aug. 2009 Revision: 1.3 41/48 ...

Page 42

... Deep Power Down. 6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands and a load mode register sequence. Elite Semiconductor Memory Technology Inc. M52D128168A Publication Date: Aug. 2009 Revision: 1.3 42/48 ...

Page 43

... CKE going high to complete self refresh exit. RFC 7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. Elite Semiconductor Memory Technology Inc. M52D128168A is required before exit from self refresh. RAS Publication Date: Aug. 2009 Revision: 1.3 ...

Page 44

... M52D128168A ...

Page 45

... D 22.22 BSC E 11.76 BSC 10.16 BSC L 0.40 0.50 0.60 0.016 0.020 0.024 L1 0.80 REF e 0.80 BSC Θ 0° 10° M52D128168A SEE DETAIL 0.21 REF 0.665 REF A 1 -C- - Dimension in inch Min Norm Max 0.047 0.018 0.008 0.875 BSC 0.463 BSC ...

Page 46

... Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in mm Dimension in inch Min Norm Max Min 1.00 0.20 0.25 0.30 0.008 0.61 0.66 0.71 0.024 0.30 0.35 0.40 0.012 7.90 8.00 8.10 0.311 7.90 8.00 8.10 0.311 6.40 6.40 0.80 M52D128168A Norm Max 0.039 0.010 0.012 0.026 0.028 0.014 0.016 0.315 0.319 0.315 0.319 0.252 0.252 0.031 Publication Date: Aug. 2009 Revision: 1.3 46/48 ...

Page 47

... Add Speed -7 spec. 2007.10.08 2. Modify I spec. CC 2007.11.16 Modify t spec. SAC 1. Move Revision History to the last 2. Correct LVTTL to LVCMOS 2009.08.18 3. Add the description of Deep Power Down Mode 4. Correct A9 bit of MRS 5. Modify the description about self refresh operation M52D128168A Description Publication Date: Aug. 2009 Revision: 1.3 47/48 ...

Page 48

... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M52D128168A Publication Date: Aug. 2009 Revision: 1.3 48/48 ...

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